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參數(shù)資料
| 型號： | 65C256 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32K x 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 32K的× 8低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 74K |
| 代理商： | 65C256 |
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
03/24/04
7
IS65C256
ISSI
WRITE CYCLE NO. 2
(
OE
is HIGH During Write Cycle)
(1,2)
Notes:
1. The internal write time is defined by the overlap of
CS
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CS
Controlled,
OE
is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CS
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CS_WR1.eps
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CS
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CS_WR2.eps
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