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參數(shù)資料
| 型號(hào)： | 65C256 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32K x 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 32K的× 8低功耗CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | 65C256 |
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
03/24/04
IS65C256
ISSI
READ CYCLE NO. 2
(1,3)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACS
t
LZCS
t
HZOE
HIGH-Z
DATA VALID
ADDRESS
OE
CS
D
OUT
t
HZCS
CS_RD2.eps
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CS
= V
IL
.
3. Address is valid prior to or coincident with
CS
LOW transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-20 ns
Min.
Symbol
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
Parameter
Max.
Unit
Write Cycle Time
20
—
ns
CS
to Write End
13
—
ns
Address Setup Time to Write End
15
—
ns
Address Hold from Write End
1
—
ns
Address Setup Time
0
—
ns
WE
Pulse Width
13
—
ns
Data Setup to Write End
10
—
ns
Data Hold from Write End
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CS
LOW and
WE
LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the write.
4. Tested with
OE
HIGH.
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