
Rev. 2.0, 03/02, page 290 of 298
Item
Page
Revisions (See Manual for Details)
Rev.
7.2.4 Flash Memory
Enable Register (FENR)
79
Description amended.
Bit 7 (FLSHE) in FENR enables or disables the CPU
access to the flash memory control registers,
FLMCR1, FLMCR2, and EBR1.
2.0
7.3 On-Board
Programming Modes
Table 7.1 Setting
Programming Modes
79
Description amended.
EIOT_0
→
E10T_0
2.0
7.3.1 Boot Mode
Table 7.2 Boot Mode
Operation
81
Changed.
Communication Contents
Processing Contents
Host Operation
LSI Operation
Processing Contents
Continat specified bit rate.
Branches to boot program at reset-start.
Boot program initiation
H'00, H'00 . . . H'00
H'00
H'55
Transmis received error-free.
H'XX
Echoback
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Transmits 1-byte of programming
H'AA reception
H'AA reception
Upper bytes, lower bytes
Echoback
H'AA
H'AA
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Transmits data H'AA to host when data H'55
is received.
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
H'FF
Boot program
erase error
I
B
Measures low-level period of receive data
H'00.
Calculates bit rate and sets BRR in SCI3.
Transmits data H'00 to host as adjustment
end indication.
B
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
T
p
F
2.0
7.4.1 Program/Program-
Verify
83
Description amended.
7. For a dummy write to a verify address, write 1-
byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words or in
longwords from the address to which a dummy
write was performed.
2.0