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參數(shù)資料
| 型號(hào)： | 5962-9203102MEA |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.1 A SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 419K |
| 代理商： | 5962-9203102MEA |
5
UC1524
UC2524
UC3524
Oscillator
The oscillator controls the frequency of the UC1524 and is
programmed by RT and CT according to the approximate
formula:
f
RC
TT
′
1.18
where
RT is in k
where
CT is in mF
where
f is in kHz
Practical values of CT fall between 0.001mF and 0.1mF.
Practical values of RT fall between 1.8k and 100k.
This results in a frequency range typically from 120Hz to
500kHz.
Blanking
The output pulse of the oscillator is used as a blanking
pulse at the output. This pulse width is controlled by the
value of CT. If small values of CT are required for fre-
quency control, the oscillator output pulse width may still
be increased by applying a shunt capacitance of up to
100pF from pin 3 to ground. If still greater dead-time is
required, it should be accomplished by limiting the maxi-
mum duty cycle by clamping the output of the error ampli-
fier. This can easily be done with the circuit in Figure 1:
Synchronous Operation
When an external clock is desired, a clock pulse of ap-
proximately 3V can be applied directly to the oscillator
output terminal. The impedance to ground at this point is
approximately 2k
. In this configuration RT CT must be
selected for a clock period slightly greater than that of the
external clock.
If two or more UC1524 regulators are to operated synchro-
nously, all oscillator output terminals should be tied to-
gether, all CT terminals connected to single timing
capacitor, and the timing resistor connected to a single RT,
terminal. The other RT terminals can be left open or shorted
to VREF. Minimum lead lengths should be used between
the CT terminals.
APPLICATION INFORMATION
16
V
REF
COMP
5k
9
GND
8
1N916
Figure 1. Error amplifier clamp.
Figure 2. Single-ended LC switching regulator circuit.
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