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參數(shù)資料
| 型號(hào)： | 5962-9203102MEA |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.1 A SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 419K |
| 代理商： | 5962-9203102MEA |
3
UC1524
UC2524
UC3524
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to +125°C
for the UC1524, –25°C to +85°C for the UC2524, and 0°C to +70°C for the UC3524, VIN = 20V, and f = 20kHz,
TA =TJ.
PARAMETER
TEST CONDITIONS
UC1524/UC2524
UC3524
UNITS
MIN
MAX
MIN
MAX
Error Amplifier Section (cont.)
Common Mode Rejection Ratio TJ = 25°C
70
dB
Small Signal Bandwidth
AV = 0dB, TJ = 25°C
3
MHz
Output Voltage
TJ = 25°C
0.5
3.8
0.5
3.8
V
Comparator Section
Duty-Cycle
% Each Output On
0
45
0
45
%
Input Threshold
Zero Duty-Cycle
1
V
Maximum Duty-Cycle
3.5
V
Input Bias Current
1
A
Current Limiting Section
Sense Voltage
Pin 9 = 2V with Error Amplifier
Set for Maximum Out, TJ = 25°C
190
200
210
180
200
220
mV
Sense Voltage T.C.
0.2
mV/°C
Common Mode Voltage
–1
+1
–1
+1
V
Output Section (Each Output)
Collector-Emitter Voltage
40
V
Collector Leakage Current
VCE = 40V
0.1
50
0.1
50
A
Saturation Voltage
IC = 50mA
1
2
1
2
V
Emitter Output Voltage
VIN = 20V
17
18
17
18
V
Rise Time
RC = 2k
,TJ = 25°C
0.2
s
Fall Time
RC = 2k
,TJ = 25°C
0.1
s
Total Standby Current (Note)
VIN = 40V
8
10
8
10
mA
Note: Excluding oscillator charging current, error and current limit dividers, and with outputs open.
The UC1524 is a fixed-frequency pulse-width-modulation
voltage regulator control circuit. The regulator operates at
a frequency that is programmed by one timing resistor
(RT), and one timing capacitor (CT), RT establishes a
constant charging current for CT. This results in a linear
voltage ramp at CT, which is fed to the comparator pro-
viding linear control of the output pulse width by the error
amplifier. The UC1524 contains an on-board 5V regulator
that serves as a reference as well as powering the
UC1524’s internal control circuitry and is also useful in
supplying external support functions. This reference volt-
age is lowered externally by a resistor divider to provide a
reference within the common-mode range of the error
amplifier or an external reference may be used. The
power supply output is sensed by a second resistor di-
vider network to generate a feedback signal to the error
amplifier. The amplifier output voltage is then compared
to the linear voltage ramp at CT. The resulting modulated
pulse out of the high-gain comparator is then steered to
the appropriate output pass transistor (Q1 or Q2)bythe
pulse-steering flip-flop, which is synchronously toggled by
the oscillator output. The oscillator output pulse also
serves as a blanking pulse to assure both outputs are
never on simultaneously during the transition times. The
width of the blanking pulse is controlled by the valve of
CT. The outputs may be applied in a push-pull configura-
tion in which their frequency is half that of the base oscil-
lator, or paralleled for single-ended applications in which
the frequency is equal to that of the oscillator. The output
of the error amplifier shares a common input to the com-
parator with the current limiting and shutdown circuitry
and can be overridden by signals from either of these in-
puts. This common point is also available externally and
may be employed to control the gain of, or to compen-
sate, the error amplifier or to provide additional control to
the regulator.
PRINCIPLES OF OPERATION
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