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| 型號(hào)： | 5891 |
| 英文描述： | BIMOS II 8-BIT SERIAL-INPUT. LATCHED SOURCE DRIVERS |
| 中文描述： | BIMOS II 8位串行輸入。鎖存源極驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 150K |
| 代理商： | 5891 |
5890
AND
5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Serial
Data
Input
Shift Register Contents
Serial
Data
Output
Latch Contents
Output Contents
Clock
Input I
1
Strobe
Input
Output
Enable
I
2
I
3
...
I
N-1
I
N
I
1
I
2
I
3
...
I
N-1
I
N
I
1
I
2
I
3
... I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
X
H
X
P
1
...
P
2
X
P
3
X
...
H
P
N-1
P
N
L
L
L
P
1
P
2
P
3
... P
N-1
P
N
... L
L
X
L
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high,
all of the output buffers are disabled (off) without
affecting the information stored in the latches or
shift register. With the OUTPUT ENABLE input
low, the outputs are controlled by the state of
their respective latches.
Dwg. No. A-12,649A
TIMING REQUIREMENTS
(T
A
= +25
°
C,V
DD
= 5 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time)..........................................................................
75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) .............................................................................
75 ns
C.
Minimum Data Pulse Width ................................................................
150 ns
D.
Minimum Clock Pulse Width...............................................................
150 ns
E.
Minimum Time Between Clock Activation and Strobe .......................
300 ns
F.
Minimum Strobe Pulse Width .............................................................
100 ns
G.
Typical Time Between Strobe Activation and
Output Transistion .........................................................................
500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
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