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參數(shù)資料
| 型號： | 550CD74M1758BGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 74.1758 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT, SMD, 6 PIN |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 556K |
| 代理商： | 550CD74M1758BGR |
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Si550
2
Rev. 0.5
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Voltage1
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
1.8 V option
1.71
1.8
1.89
Supply Current
IDD
Output enabled
LVPECL
CML
LVDS
CMOS
—
120
108
99
90
130
117
108
98
mA
TriState mode
—
60
70
Output Enable (OE)2
VIH
0.75 x VDD
——
V
VIL
——
0.5
Operating Temperature Range3
TA
–40
—
85
C
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE pin includes a 17 k
pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
3. If the device is powered up below –20 C and the ambient temperature rises by approximately 105 C during normal
operation, the device will perform a one-time recalibration. The output is squelched for approximately 2–3 ms during
this recalibration.
Table 2. VC Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Control Voltage Tuning Slope1,2,3
KV
10 to 90% of VDD
—45
90
135
180
—
ppm/V
Control Voltage Linearity4
LVC
BSL
–5
±1
+5
%
Incremental
–10
±5
+10
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
ZVC
500
—
k
Nominal Control Voltage
VCNOM
@ fO
—3/8 x VDD
—V
Control Voltage Tuning Range
VC
0VDD
V
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 7.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±28% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 550CD74M1758DG | 制造商:Silicon Laboratories Inc 功能描述: |
| 550CD74M1758DGR | 制造商:Silicon Laboratories Inc 功能描述:CONTROLLED OSCILLATOR 74.1758MHZ VCXO CM 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 74.1758MHZ VCXO CMOS 6SMD - Tape and Reel |
| 550CD74M2500DGR | 功能描述:74.25MHz CMOS VCXO Oscillator Surface Mount 3.3V 98mA Enable/Disable 制造商:silicon labs 系列:Si550 包裝:帶卷（TR） 零件狀態(tài):有效 類型:VCXO 頻率:74.25MHz 功能:啟用/禁用 輸出:CMOS 電壓 - 電源:3.3V 頻率穩(wěn)定度:±50ppm 工作溫度:-40°C ~ 85°C 電流 - 電源（最大值）:98mA 等級:- 安裝類型:表面貼裝 大小/尺寸:0.276" 長 x 0.197" 寬（7.00mm x 5.00mm） 高度:0.071"（1.80mm） 封裝/外殼:6-SMD，無引線（DFN，LCC） 電流 - 電源（禁用）（最大值）:75mA 標準包裝:250 |
| 550CD77M7600DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 77.76MHZ VCXO CMOS 6SMD - Trays |
| 550CD77M7600DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 77.76MHZ VCXO CMOS 6SMD - Tape and Reel |
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