參數(shù)資料
型號(hào): 48SD3208RPFK
廠商: MAXWELL TECHNOLOGIES
元件分類: DRAM
英文描述: CAP 1.5UF 50V CERAMIC MONO 20%
中文描述: 32M X 8 SYNCHRONOUS DRAM, 6 ns, PDFP72
封裝: DFP-72
文件頁(yè)數(shù): 38/39頁(yè)
文件大?。?/td> 589K
代理商: 48SD3208RPFK
48SD3208
M
em
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ry
8
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (8-Meg X 8-Bit X 4-Banks) SDRAM
01.10.05 Rev 2
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins:
Note: H: V
IH L: VIL x VIH or VIL V: Valid address input
Ignore command (DESL): When this command is set (CS = High), the SDRAM ignores command input at
the clock. However, the internal status is held.
No Operation (NOP): This command is not an execution command. However, the internal operations
continue.
Column address strobe and read command (READ): This command starts a read operation. In addition,
the start address of a burst read is determined by the column address (AY0 to AY9) and the bank select
address (BS). After the read operation, the output buffer becomes High-Z.
Read with auto-precharge (READ A): This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4, or 8.
COMMAND
SYMBOL
N
-1
N
CS
RAS
CAS
WE
BA0/
BA1
A10
A0 TO
A12
Ignore command
DESL
H
x
H
x
No Operation
NOP
H
x
L
H
x
Column Address and
Read command
READ
H
x
LH
V
L
V
Read with auto-pre-
charge
READ A
H
x
L
H
L
H
V
H
V
Column Address and
write command
WRIT
H
x
L
H
L
V
L
V
Write with auto-pre-
charge
WRIT A
H
x
L
H
L
V
H
V
Row address strobe
and bank active
ACTV
H
x
L
H
V
Precharge select
bank
PRE
H
x
L
H
L
V
L
x
Precharge all banks
PALL
H
x
L
H
L
x
H
x
Refresh
REF/
SELF
H
LLLL
H
x
Mode register set
MRS
H
x
LLLL
V
相關(guān)PDF資料
PDF描述
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