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參數(shù)資料
| 型號： | 48SD3208RPFK |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | CAP 1.5UF 50V CERAMIC MONO 20% |
| 中文描述： | 32M X 8 SYNCHRONOUS DRAM, 6 ns, PDFP72 |
| 封裝： | DFP-72 |
| 文件頁數(shù)： | 35/39頁 |
| 文件大?。?/td> | 589K |
| 代理商： | 48SD3208RPFK |
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48SD3208
M
em
o
ry
5
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (8-Meg X 8-Bit X 4-Banks) SDRAM
01.10.05 Rev 2
TABLE 5. AC Electrical Characteristics
(V
CC =3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125° C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYP
MAX
UNIT
System clock cycle time1
(CAS latency = 2)
(CAS latency = 3)
t
CK
9, 10, 11
10
7.5
ns
CLK high pulse width1,7
t
CKH
9, 10, 11
2.5
ns
CLK low pulse width1,7
t
CKL
9, 10, 11
2.5
ns
Access time from CLK1,2
(CAS latency = 2)
(CAS latency = 3)
t
AC
9, 10, 11
6
ns
Data-out hold time1,2
t
OH
9, 10, 11
2.7
ns
CLK to Data-out low impedance1,2,3,7
t
LZ
9, 10, 11
2
ns
CLK to Data-out high impedance1,4,7
(CAS latency = 2, 3)
t
HZ
9, 10, 11
5.4
ns
Input setup time 1, 5,6
t
AS, tCS,
t
DS, tCES
9, 10, 11
1.5
ns
CKE setup time for power down exit1
t
CESP
9, 10, 11
1.5
ns
Input hold time1,6
t
AH, tCH, tDH
t
CEH
9, 10, 11
1.5
ns
Ref/Active to Ref/Active command period1
t
RC
9, 10, 11
70
ns
Active to Precharge command period1
t
RAS
9, 10, 11
50
120000
ns
Active command to column command
(same bank)1
t
RCD
9, 10, 11
20
ns
Precharge to Active command period1
t
RP
9, 10, 11
20
ns
Write recovery or data-in to precharge lead time1
t
DPL
9, 10, 11
20
ns
Active( a) to Active (b) command period1
t
RRD
9, 10, 11
20
ns
Transition time(rise and fall)7
t
T
9, 10, 11
1
5
ns
Refresh Period
t
REF
9, 10, 11
16
6.4
ms
@ 105 °C32
168
@ 85 °C64
@ 70 °C
128
1. AC measurement assumes t
T=1ns. Reference level for timing of output signals is 1.5V.
2. Access time is measured at 1.5V.
3. t
LZ(min) defines the time at which the outputs achieve the low impedance state.
4. t
HZ defienes the time at which the outputs achieve the high impedance state.
5. t
CES defines CKE setup time to CLK rising edge except for the power down exit command.
6. t
AS/tAH: Address, tCS/tCH: /CS, /RAS, /CAS, /WE, DQM
7. Guarenteed by design. (Not tested)
8. Guarenteed by Device Characterization Testing. (Not 100% Tested)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 48SD3208RPFE | 256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
| 48SD3208RPFH | 256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
| 48SD3208RPFI | CAP 1.5UF 50V CERAMIC MONO 20% |
| 48SD3208 | 256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks |
| 48SD6404RPFE | CAP 1200PF 100V CERAMIC MONO 5% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 48SD6404 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
| 48SD6404RPFK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks |
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