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參數(shù)資料
| 型號： | 45DB041B |
| 廠商： | Atmel Corp. |
| 英文描述： | 4-megabit 2.5-volt Only or 2.7-volt Only DataFlash |
| 中文描述： | 4兆位2.5伏，只有2.7伏，只有上DataFlash |
| 文件頁數(shù)： | 29/33頁 |
| 文件大?。?/td> | 233K |
| 代理商： | 45DB041B |
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5
AT45DB041B
1938F–DFLSH–10/02
loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the
status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the
next eight clock cycles. The five most significant bits of the status register will contain
device information, while the remaining three least-significant bits are reserved for future
use and will have undefined values. After bit 0 of the status register has been shifted
out, the sequence will repeat itself (as long as CS remains low and SCK is being tog-
gled) starting again with bit 7. The data in the status register is constantly updated, so
each repeating sequence will output new data.
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
device is in a busy state. The user can continuously poll bit 7 of the status register by
stopping SCK at a low level once bit 7 has been output. The status of bit 7 will continue
to be output on the SO pin, and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can cause the device to be in a
busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Com-
pare, Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory
Page Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page
Program, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indi-
cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the
main memory page does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the
AT45DB041B, the four bits are 0, 1, 1 and 1. The decimal value of these four binary bits
does not equate to the device density; the four bits represent a combinational code
relating to differing densities of Serial DataFlash devices, allowing a total of sixteen dif-
ferent density configurations.
Program and Erase
Commands
BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2.
To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, must
be followed by 15 don’t care bits and nine address bits (BFA8 - BFA0). The nine
address bits specify the first byte in the buffer to be written. The data is entered following
the address bits. If the end of the data buffer is reached, the device will wrap around
back to the beginning of the buffer. Data will continue to be loaded into the buffer until a
low-to-high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written
into either buffer 1 or buffer 2 can be programmed into the main memory. To start the
operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be followed by the
four reserved bits, 11 address bits (PA10 - PA0) that specify the page in the main
memory to be written, and nine additional don’t care bits. When a low-to-high transition
occurs on the CS pin, the part will first erase the selected page in main memory to all 1s
and then program the data stored in the buffer into the specified page in the main mem-
ory. Both the erase and the programming of the page are internally self-timed and
should take place in a maximum time of t
EP. During this time, the status register will indi-
cate that the part is busy.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY/BUSY
COMP
0
111
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 45DB081B | AT-45DB081B DATA FLASH RELIABILITY DATA |
| 45IZ | 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 45L(R)SERIES | Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits |
| 45L(R) | STANDARD RECOVERY DIODES Stud Version |
| 45L100 | Standard Recovery Diodes(標(biāo)準(zhǔn)修復(fù)二極管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 45DB081B | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT-45DB081B DATA FLASH RELIABILITY DATA |
| 45DB081B-CNC | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 45DB161B | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:16M bit dataflash 2.7V |
| 45DB642DCNU | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 45DB642D-CNU | 制造商: 功能描述: 制造商:undefined 功能描述: |
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