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參數(shù)資料
| 型號： | 4565B2 |
| 廠商： | LSI CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909 |
| 封裝： | PLASTIC, BGA-909 |
| 文件頁數(shù)： | 50/61頁 |
| 文件大?。?/td> | 1691K |
| 代理商： | 4565B2 |
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4565B Ultramapper Full Transport Retiming Device
Hardware Design Guide, Revision 2
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
December 17, 2003
54
Agere Systems Inc.
7.2 Synchronous Read Mode
Notes:
MPCLK
Input clock to 4565B Ultramapper Full Transport Retiming Device MPU block.
ADDR [20:0]
The address will be available throughout the entire cycle, and must be stable before ADSN turns high.
CSN (Input)
Chip select is an active-low signal.
ADSN (Input) Address strobe is active-low. ADSN must be one MPCLK clock period wide.
RWN (Input)
The read (H) write (L) signal is always high during the read cycle.
DTN (Output) Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one clock, and then driven high before
entering a high-impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state term.) DTN will become
3-stated when CSN is high. Typically, DTN is active four or five MPCLK cycles after ADSN is low.
DATA [15:0]
Read data is stable in Tn – 1.
Figure 7-2. Microprocessor Interface Synchronous Read Cycle—MPMODE Pin = 1
* If DTN is used, then the maximum frequency for MPCLK is determined by the processor’s setup specification for DTN. MPU maximum bus operating
frequency = 1/(MPU DTN setup time + tDNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection.
DTN fall is variable, depending on the block selected for access and in some cases the state of the SONET frame. This interval is typically in the 100 ns
to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns. Certain registers in the VTMPR block have a
very long acknowledge cycle (in the order of 32 MPCLK cycles). The reason for this is that those registers can also be accessed by the VTMPR lower
order path overhead interface as part of SONET overhead termination functions. Therefore, the user must insert long enough delay or use the DTN sig-
nal to read/write these registers correctly.
Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications
Symbol
Parameter
Setup
(Min)
Hold
(Min)
Delay
(Min)
Delay
(Max)
Unit
MPCLK
MPCLK 16 MHz Min—66* MHz Max Frequency
————
ns
tAVS
ADDR Valid to MPCLK
3.5
—
ns
tAPD
MPCLK to ADDR Invalid
—
0
—
ns
tCSNSU
CSN Active to MPCLK
6
—
ns
tADSNSU
ADSN Valid to MPCLK
6
—
ns
tSNIPD
MPCLK to ADSN Inactive
—
0
—
ns
tDNVPD
MPCLK to DTN Valid
—
2.5
12
ns
tDNIPD
MPCLK to DTN Invalid
—
2.5
12
ns
tDAIPD
MPCLK to DATA 3-state
—
3.5
15
ns
tADSNVDTF ADSN Valid to DTN Falling
—
—
ns
MPCLK
ADDR[20:0]
CSN
ADSN
RWN
tADSNSU
tSNIPD
tCSNSU
tAVS
T0
T1
T2
Tn – 4
Tn – 3
Tn – 2
Tn – 1
Tn
DTN
DATA[15:0]
(OUTPUT)
tDAIPD
tDNVPD
tDNIPD
tADSNVDTF
HIGH Z
tAPD
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