參數(shù)資料
型號(hào)： 4565B2
廠商： LSI CORP
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 38/61頁(yè)
文件大?。?/td> 1691K
代理商： 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
43
5.6 NSMI Timing
Figure 5-12. NSMI Clock and Data Timing for the STS-1 Mode
Figure 5-13. NSMI Clock and Data Diagram for SPEMPR NSMI Mode
160,7;&/.
tPD
W68
W+
NSMIRXCLK
NSMIRXDATA
NSMITXDATA
NSMI_TXDATAEN
(output)
NSMI_TXCLK
(51.84 MHz output)
SONET Frame
(for info only)
NSMI_TXDATA
(output)
NSMI_TXSYNC
(output)
NSMI_RXCLK
(51.84 MHz output)
SONET Frame
(for info only)
NSMI_RXDATA
(input)
NSMI_RXSYNC
(Output)
Position of above pulse is provisionable 0-89 bytes + 0-7 bits before J1
Note: Tx and Rx J1 are not aligned. Transmit path pointer is fixed at 522.
NSMI_RXDATAEN
(output)
125
s
Position of above pulse is provisionable 0
-89 bytes + 0-7 bits before J1
125
s
Separation depends on pointer
Z3
89 Columns
Z4
TOH
J1
TOH
C2
TOH
Z4
89 Columns
J1
TOH
C2
TOH
G1
TOH
Notes:
Clock from SPEMPR is at 51.84 MHz rate and is not gapped. TXDATAEN is provided to mark the POH time of the SPE.
J1 can occur anywhere in the frame and its position is optionally marked by TXSYNC, which is provisioned to be N columns (bytes) plus
M bits earlier in time than J1.
During periods where the POH is present, the TXDATAEN signal goes high.
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