參數(shù)資料
型號(hào)： 4250
英文描述： Low-Cost, 2.7V to 5.5V Temperature Switches in a SOT23
中文描述： 4250組數(shù)據(jù)表數(shù)據(jù)表652K/NOV.30.97
文件頁(yè)數(shù)： 24/59頁(yè)
文件大小： 652K
代理商： 4250
23
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(5) Timer output pin (G
1
/T
OUT
)
Timer output pin (G
1
/T
OUT
) has the function to output the timer
1 underflow signal divided by 2. The selection of G
1
/T
OUT
pin
function can be controlled with the bit 3 of register V1.
(6) Timer interrupt request flag (T1F)
Timer interrupt request flag is set to “1” when the timer
underflows. The state of this flag can be examined with the
skip instruction (SNZ1).
Use the register V1 to select an interrupt or a skip instruction.
T1F flag is cleared to “0” when an interrupt occurs or when the
next instruction is skipped with a skip instruction.
(1) Control registers related to timer
Timer control register V1
G
1
/T
OUT
pin function selection bit and prescaler/timer 1
operation start bit are assigned to register V1. Set the
contents of this register through register A with the TV1A
instruction. The TAV1 instruction can be used to transfer
the contents of register V1 to register A.
Key-on wakeup control register K0
Prescaler dividing ratio selection bit is assigned to register
K0. Set the contents of this register through register A with
the TK0A instruction. The TAK0 instruction can be used to
transfer the contents of register K0 to register A.
(2) Precautions
Note the following for the use of timers.
Prescaler
Stop the prescaler operation to change its frequency dividing
ratio.
Reading the count value
Stop timer 1 counting and then execute the TAB1 instruction
to read its data.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio
can be selected. The count source of prescaler is the
instruction clock.
Use the bit 3 of register K0 to select the prescaler dividing
ratio and the bit 2 of register V1 to start and stop its operation.
Prescaler is initialized, and the output signal (ORCLK) stops
when the bit 2 of register V1 is cleared to “0.”
(4) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1). Data can be set simultaneously in timer 1 and
the reload register (R1) with the T1AB instruction.
Timer 1 starts counting after the following process;
set data in timer 1, and
set the bit 2 of register V1 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 interrupt request flag (T1F) is set to “1,” new data is
loaded from reload register R1, and count continues (auto-
reload function).
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 1 to registers A and B with the
TAB1 instruction. When reading the data, stop the counter
and then execute the TAB1 instruction. Timer 1 underflow
signal divided by 2 can be output from G
1
/T
OUT
pin.
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