參數資料
型號: 3256E
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable High Density PLD
中文描述: 在系統(tǒng)可編程高密度可編程邏輯器件
文件頁數: 9/15頁
文件大?。?/td> 159K
代理商: 3256E
Specifications
ispLSI 3256E
9
ispLSI 3256E Timing Model
Note: Calculations are based upon timing specifications for the ispLSI 3256E-100L.
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
4 PT Bypass
#32
20 PT
XOR Delays
Control
PTs
#41 - 43
Input
Register
RST
I/O Pin
(Input)
Y0,1,2
Y3,4
D
Q
GRP
#30
GLB Reg Bypass
#36
ORP Bypass
#45
D
Q
RST
RE
OE
CK
I/O Reg Bypass
#24
I/O Cell
ORP
GLB
GRP
I/O Cell
#25 - 29
#31
#33 - 35
#50
#53
#54
#44
Reset
#51
#52
#52
#37 - 40
#48, 49
#46, 47
GOE0,1
TOE
0902/3256E
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
=
=
=
=
(2.4 + 2.3 + 4.1) + (0.3) - (2.4 + 2.3 + 3.0)
1.4 ns
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
iobp +
t
grp +
t
ptck(min))
(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
iobp +
t
grp +
t
20ptxor)
(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)
(2.4 + 2.3 + 3.6) + (5.0) - (2.4 + 2.3 + 4.1)
4.5 ns
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
iobp +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#24 + #30 + #43) + (#39) + (#44 + #46)
(2.4 + 2.3 + 3.6) + (1.6) + (1.2 + 2.6)
13.7 ns
Table 2- 0042-3256E
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