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參數(shù)資料
| 型號： | 3256A |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 163K |
| 代理商： | 3256A |
Specifications
ispLSI 3256A
6
UA
–
–
–
NI
24.5
13.5
13.5
23.0
23.0
External Switching Characteristics
1, 2, 3
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
toeen
t
toedis
t
wh
t
wl
t
su3
t
h3
UNITS
-70
MIN.
–
–
77.0
TEST
COND.
1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4.
f
max (Toggle) may be less than 1/(
t
wh +
t
wl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
Table 2-0030C/3256A
1
5
3
1
( )
-50
MIN.
–
–
57.0
MAX.
15.0
18.0
MAX.
20.0
24.5
DESCRIPTION
#
2
PARAMETER
A
A
A
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
2 Data Prop. Delay
3 Clk Frequency with Internal Feedback
ns
ns
MHz
–
–
–
–
–
A
–
4 Clk Frequency with Ext. Feedback
5 Clk Frequency, Max. Toggle
6 GLB Reg. Setup Time before Clk, 4 PT Bypass
7 GLB Reg. Clk to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clk, 4 PT Bypass
–
–
–
–
–
–
MHz
MHz
ns
ns
ns
4
9.0
–
–
–
–
–
–
A
–
B
C
B
C
B
C
9 GLB Reg. Setup Time before Clk
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 Test OE Output Enable
19 Test OE Output Disable
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
20 Ext. Synchronous Clk Pulse Duration, High
21 Ext. Synchronous Clk Pulse Duration, Low
22 I/O Reg Setup Time before Ext. Sync Clk (Y3, Y4)
23 I/O Reg Hold Time after Ext. Sync Clk (Y3, Y4)
6.0
6.0
5.0
0.0
–
–
–
–
–
–
–
–
ns
ns
ns
ns
50.0
83.0
9.5
–
0.0
11.0
0.0
10.0
10.5
15.0
18.0
18.0
11.0
11.0
17.0
17.0
37.0
63.0
12.5
0.0
15.0
0.0
13.5
8.0
8.0
7.0
0.0
12.0
14.0
20.0
24.5
-90
MIN. MAX.
–
–
90.0
12.0
15.0
–
–
–
–
7.5
–
–
–
–
–
–
–
–
–
–
–
–
4.0
4.0
5.0
0.0
–
–
–
–
61.0
125
8.0
–
0.0
9.0
0.0
6.5
9.0
13.5
16.0
16.0
10.0
10.0
10.0
10.0
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| 3256E | In-System Programmable High Density PLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3256E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| 3256TT | 功能描述:1-1/16'' BROAD BULL PIN WITH TET 制造商:klein tools, inc. 系列:- 零件狀態(tài):在售 工具類型:牛角插針 配套使用產(chǎn)品/相關(guān)產(chǎn)品:定位孔 重量:1.5 磅（680.4g） 標準包裝:3 |
| 3257 | 功能描述:塑料硬件 SW 2 SNUB BUSHING RoHS:否 制造商:3M Electronic Specialty 類型:Cylindrical Bumpers |
| 3257.0321 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HANDLE LEG OFFSET NAT 32MM |
| 3257.0323 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HANDLE LEG OFFSET BLK 32MM PK2 |
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