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參數(shù)資料
| 型號(hào)： | 3239-00 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2.2 GHz Integer-N PLL for Low Phase Noise Applications |
| 中文描述： | 2.2 GHz的整數(shù)N的低相位噪聲鎖相環(huán)的應(yīng)用 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 221K |
| 代理商： | 3239-00 |
PE3239
Product Specification
Main Counter Chain
Copyright
Peregrine Semiconductor Corp. 2001
Page 8 of 13
File No. 70/0047~01A
|
UTSi
CMOS RFIC SOLUTIONS
The main counter chain divides the RF input
frequency, F
in
, by an integer derived from the user
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9 bit M counter. Setting
Pre_en
“l(fā)ow” enables the 10/11 prescaler. Setting
Pre_en
“high” allows F
in
to bypass the prescaler
and powers down the prescaler.
The output from the main counter chain, f
p
, is
related to the VCO frequency, F
in
, by the following
equation:
f
p
= F
in
/ [10 x (M + 1) + A] (1)
where A
≤
M + 1, M
≠
0
When the loop is locked, F
in
is related to the
reference frequency, f
r
, by the following equation:
F
in
= [10 x (M + 1) + A] x (f
r
/ (R+1)) (2)
where A
≤
M + 1, M
≠
0
A consequence of the upper limit on A is that F
in
must be greater than or equal to 90 x (f
r
/ (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
Reference Counter
The reference counter chain divides the reference
frequency, f
r
, down to the phase detector
comparison frequency, f
c
.
The output frequency of the 6 bit R Counter is
related to the reference frequency by the following
equation:
f
c
= f
r
/ (R + 1) (3)
where R > 0
Note that programming R equal to “0” will pass the
reference frequency, f
r
, directly to the phase
detector.
Register Programming
Serial Interface Mode
While the E_WR input is “l(fā)ow” and the S_WR input
is “l(fā)ow”, serial input data (Sdata input), B
0
to B
19
,
are clocked serially into the primary register on the
rising edge of Sclk, MSB (B
0
) first. The contents
from the primary register are transferred into the
secondary register on the rising edge of either
S_WR according to the timing diagrams shown in
Figure 6. Data are transferred to the counters as
shown in Table 7 on page 9.
The double buffering provided by the primary and
secondary registers allows for “ping-pong” counter
control using the FSELS input. When FSELS is
“high”, the primary register contents set the counter
inputs. When FSELS is “l(fā)ow”, the secondary
register contents are utilized.
While the E_WR input is “high” and the S_WR input
is “l(fā)ow”, serial input data (Sdata input), B
0
to B
7
, are
clocked serially into the enhancement register on
the rising edge of Sclk, MSB (B
0
) first. The
enhancement register is double buffered to prevent
inadvertent control changes during serial loading,
with buffer capture of the serially entered data
performed on the falling edge of E_WR according to
the timing diagram shown in Figure 6. After the
falling edge of E_WR, the data provide control bits
as shown in Table 8 on page 9 will have their bit
functionality enabled by asserting the
Enh
input
“l(fā)ow”.
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