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參數(shù)資料
| 型號(hào)： | 3239-00 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2.2 GHz Integer-N PLL for Low Phase Noise Applications |
| 中文描述： | 2.2 GHz的整數(shù)N的低相位噪聲鎖相環(huán)的應(yīng)用 |
| 文件頁(yè)數(shù)： | 5/13頁(yè) |
| 文件大?。?/td> | 221K |
| 代理商： | 3239-00 |
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PE3239
Product Specification
Table 6. AC Characteristics
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2001
Page 5 of 13
V
DD
= 3.0 V, -40
°
C < T
A
< 85
°
C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 5, 6, 7)
f
Clk
Serial data clock frequency
(Note 1)
10
MHz
t
ClkH
Serial clock HIGH time
30
ns
t
ClkL
Serial clock LOW time
30
ns
t
DSU
Sdata set-up time to Sclk rising edge
10
ns
t
DHLD
Sdata hold time after Sclk rising edge
10
ns
t
PW
S_WR pulse width
30
ns
t
CWR
Sclk rising edge to S_WR rising edge
30
ns
t
CE
Sclk falling edge to E_WR transition
30
ns
t
WRC
S_WR falling edge to Sclk rising edge
30
ns
t
EC
E_WR transition to Sclk rising edge
30
ns
Main Divider (Including Prescaler)
F
in
Operating frequency
200
2200
MHz
P
Fin
Input level range
External AC coupling
-5
5
dBm
Main Divider (Prescaler Bypassed)
F
in
Operating frequency
20
220
MHz
P
Fin
Input level range
External AC coupling
-5
5
dBm
Reference Divider
f
r
Operating frequency
(Note 3)
100
MHz
P
fr
Reference input power (Note 2)
Single ended input
-2
dBm
Phase Detector
f
c
Comparison frequency
(Note 3)
20
MHz
Note 1:
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
Note 2:
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase
noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Note 3:
Parameter is guaranteed through characterization only and is not tested.
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