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參數(shù)資料
| 型號(hào)： | 30144-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, PBGA352 |
| 封裝： | BGA-352 |
| 文件頁(yè)數(shù)： | 148/247頁(yè) |
| 文件大?。?/td> | 4365K |
| 代理商： | 30144-23 |
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www.national.com
148
Revision 1.1
Integrated Functions (
Continued
)
G
4.5.9
The GXLV processor utilizes a graphics memory aperture
that is up to 4 MB in size. The base address of the graph-
ics memory aperture is stored in the DRAM controller
Graphics
Base
Address
MC_GBASE_ADD register, Table 4-15 on page 116 ). The
graphics memory is made up of the normal uncom-
pressed frame buffer, compressed display buffer, and cur-
sor buffer. Each buffer begins at a programmable offset
within the graphics memory aperture.
Memory Organization Registers
register
(see
GBADD
of
The various memory buffers are arranged so as to effi-
ciently pack the data within the graphics memory aper-
ture. The arrangement is programmable to efficiently
accommodate different display modes. The cursor buffer
is a linear block so addressing is straightforward. The
frame buffer and compressed display buffer are arranged
based upon scan lines. Each scan line has a maximum
number of valid or active DWORDs, and a delta, which
when added to the previous line offset, points to the next
line. In this way, the buffers may either be stored as linear
blocks, or as logical blocks as desired.
The Memory Organization Registers group consists of six
32-bit
registers
located
at
These registers are summarized in Table 4-28 on page
141, and Table 4-30 gives their bit formats.
GX_BASE+8310h-8328h.
Table 4-30. Display Controller Memory Organization Registers
Bit
Name
Description
GX_BASE+8310h-8313h
DC_FB_ST_OFFSET Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:22
21:0
RSVD
FB_START
_OFFSET
Reserved:
Set to 0.
Frame Buffer Start Offset:
This value represents the byte offset from the Graphics Base Address regis-
ter (see GBADD of MC_GBASE_ADD register in Table 4-15 on page 116) of the starting location of the
displayed frame buffer. This value may be changed to achieve panning across a virtual desktop or to
allow multiple buffering.
When this register is programmed to a nonzero value, the compression logic should be disabled. The
memory address defined by bits [21:4] will take effect at the start of the next frame scan. The pixel offset
defined by bits [3:0] will take effect immediately (in general, it should only change during vertical blank-
ing).
GX_BASE+8314h-8317h
DC_CB_ST_OFFSET Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:22
21:0
RSVD
CB_START
_OFFSET
Reserved:
Set to 0.
Compressed Display Buffer Start Offset:
This value represents the byte offset from the Graphics
Base Address register (see GBADD of MC_GBASE_ADD register in Table 4-15 on page 116) of the
starting location of the compressed display buffer. Bits [3:0] must be programmed to zero so that the
start offset is aligned to a 16-byte boundary. This value should change only when a new display mode is
set due to a change in size of the frame buffer.
GX_BASE+8318h-831Bh
DC_CUR_ST_OFFSET Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:22
21:0
RSVD
Reserved:
Set to 0.
Cursor Start Offset:
This register contains the byte offset from the Graphics Base Address register (see
GBADD of MC_GBASE_ADD register in Table 4-15 on page 116) of the starting location of the cursor
display pattern. Bits [1:0] should always be programmed to zero so that the start offset is DWORD
aligned. The cursor data will be stored as a linear block of data.
CUR_START
_OFFSET
GX_BASE+831Ch-831Fh
Reserved
Default Value = 00000000h
GX_BASE+8320h-8323h
DC_VID_ST_OFFSET Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:22
21:0
RSVD
VID_START
_OFFSET
Reserved:
Set to 0.
Video Buffer Start Offset Value:
This register contains the byte offset from the Graphics Base Address
register (see GBADD of MC_GBASE_ADD register in Table 4-15 on page 116) of the starting location of
the Video Buffer Start. Bits [3:0] must be programmed as zero so that the start offset is aligned to a 16
byte boundary.
GX_BASE+8324h-8327h
DC_LINE_DELTA Register (R/W) (Locked)
Default Value = xxxxxxxxh
31:22
21:12
RSVD
CB_LINE_
DELTA
Reserved:
Set to 0.
Compressed Display Buffer Line Delta:
This value represents number of DWORDs that, when added
to the starting offset of the previous line, will point to the start of the next compressed line in memory. It
is used to always maintain a pointer to the starting offset for the compressed display buffer line being
loaded into the display FIFO.
Reserved:
Set to 0.
11:10
RSVD
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