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| 型號(hào)： | 30144-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, PBGA352 |
| 封裝： | BGA-352 |
| 文件頁(yè)數(shù)： | 102/247頁(yè) |
| 文件大?。?/td> | 4365K |
| 代理商： | 30144-23 |
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102
Revision 1.1
Integrated Functions (
Continued
)
G
4.1.5
While the majority of the GXLV
’
s integrated function inter-
face is memory mapped, a few integrated function regis-
ters are accessed via four GXLV specific instructions.
Table 4-6 shows these instructions.
Display Driver Instructions
Adding CPU instructions does not create a compatibility
problem for applications that may depend on receiving
illegal opcode traps. The solution is to make these instruc-
tions generate an illegal opcode trap unless a compatibil-
ity bit is explicitly set. The GXLV processor uses the
scratchpad size field (bits [3:2] in GCR, Index B8h) to
enable or disable all of the graphics instructions.
Note:
If the scratchpad size bits are zero, meaning that
none of the cache is defined as scratchpad, then
hardware will assume that the graphics controller
is not being used and the graphics instructions
will be disabled.
Any other scratchpad size will enable all of the new
instructions. Note that the base address of the memory
map in the GCR register can still be set up to allow access
to the memory controller registers
4.1.6
The GXLV processor has several internal registers that
control the BLT buffer and power management circuitry in
the dedicated cache subsystem. To avoid adding addi-
tional instructions to read and write these registers, the
GXLV processor has a general mechanism to access
internal CPU registers with reasonable performance. The
GXLV processor has two special instructions to read and
write CPU registers: CPU_READ and CPU_WRITE. Both
instructions fetch a 32-bit register address from
EBX
as
shown in Table 4-6 and Table 4-7
.
CPU_WRITE uses
EAX
for the source data, and CPU_READ uses
EAX
as the
destination. Both instructions always transfer 32 bits of
data.
CPU_READ/CPU_WRITE Instructions
These instructions work by initiating a special I/O transac-
tion where the high address bit is set. This provides a very
large address space for internal CPU registers.
The BLT buffer base registers define the starting physical
addresses of the BLT buffers located within the dedicated
L1 cache. The dedicated cache can be configured for up
to 4 KB, so 12 address bits are required for each base
address.
.
Table 4-6. Display Driver Instructions
Syntax
Opcode
Registers
Description
BB0_RESET
0F3A
N/A
Reset the BLT Buffer 0 pointer to the base.
BB1_RESET
0F3B
N/A
Reset the BLT Buffer 1 pointer to the base.
CPU_WRITE
0F3C
EBX = Register Address (see Table 4-7)
EAX = Source Data
Write data to CPU internal register.
CPU_READ
0F3D
EBX = Register Address (see Table 4-7)
EAX = Destination Data
Read data from CPU internal register.
Table 4-7. Address Map for CPU-Access Registers
Register
EBX Address
Description
L1_BB0_BASE
FFFFFF0Ch
BLT Buffer 0 base address (see Table 4-5 on page 101).
L1_BB1_BASE
FFFFFF1Ch
BLT Buffer 1 base address (see Table 4-5 on page 101).
L1_BB0_POINTER
FFFFFF2Ch
BLT Buffer 0 pointer address (see Table 4-5 on page 101).
L1_BB1_POINTER
FFFFFF3Ch
BLT Buffer 1 pointer address (see Table 4-5 on page 101).
PM_BASE
FFFFFF6Ch
Power management base address (see Table 5-3 on page 183).
PM_MASK
FFFFFF7Ch
Power management address mask (see Table 5-3 on page 183).
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