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參數(shù)資料
| 型號(hào)： | 28F640J5 |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器) |
| 中文描述： | 5伏特英特爾StrataFlash存儲(chǔ)器（5V的6400位英特爾的StrataFlash閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 44/53頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 28F640J5 |
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28F320J5/28F640J5
E
44
PRELIMINARY
6.4 DC Characteristics
(Continued)
Sym
Parameter
Notes
Min
Max
Unit
Test Conditions
V
IL
V
IH
Input Low Voltage
7
–0.5
0.8
V
Input High Voltage
7
2.0
V
CC
+ 0.5
0.45
V
V
OL
Output Low Voltage
3,7
V
V
CCQ
= V
CCQ1
Min
I
OL
= 5.8 mA
V
CCQ
= V
CCQ2
Min
I
OL
= 2 mA
V
CCQ
= V
CCQ1
Min or V
CCQ
= V
CCQ2
Min
I
OH
= –2.5 mA (V
CCQ1
)
–2 mA (V
CCQ2
)
V
CCQ
= V
CCQ1
Min or V
CCQ
= V
CCQ2
Min
I
OH
= –2.5 mA
V
CCQ
= V
CCQ1
Min or V
CCQ
= V
CCQ2
Min
I
OH
= –100 μA
0.4
V
V
OH
Output High Voltage
3,7
2.4
V
0.85 X
V
CCQ
V
V
CCQ
–0.4
V
V
PENLK
V
PEN
Lockout during
Normal Operations
V
PENH
V
PEN
during Block
Erase, Program, or
Lock-Bit Operations
V
LKO
V
CC
Lockout Voltage
V
HH
RP# Unlock Voltage
4,7,11
3.6
V
4,11
4.5
5.5
V
8
3.25
V
9,10
11.4
12.6
V
Set master lock-bit
Override lock-bit
NOTES:
1.
All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).
Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications.
I
CCES
is specified with the device de-selected. If the device is read or written while in erase suspend mode, the device’s
current draw is I
CCR
or I
CCW
.
Includes STS.
Block erases, programming, and lock-bit configurations are inhibited when V
PEN
≤
V
PENLK
, and not guaranteed in the
range between V
PENLK
(max) and V
PENH
(min), and above V
PENH
(max).
CMOS inputs are either V
CC
± 0.2 V or GND ± 0.2 V. TTL inputs are either V
IL
or V
IH
.
Add 5 mA for V
CCQ
= V
CCQ2
min.
Sampled, not 100% tested.
Block erases, programming, and lock-bit configurations are inhibited when V
CC
< V
LKO
, and not guaranteed in the range
between V
LKO
(min) and V
CC
(min), and above V
CC
(max).
Master lock-bit set operations are inhibited when RP# = V
IH
. Block lock-bit configuration operations are inhibited when the
master lock-bit is set and RP# = V
IH
. Block erases and programming are inhibited when the corresponding block-lock bit
is set and RP# = V
IH
. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
attempted with V
IH
< RP# < V
HH
.
RP# connection to a V
HH
supply is allowed for a maximum cumulative period of 80 hours.
Tie V
PEN
to V
CC
(4.5 V–5.5 V).
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
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