參數(shù)資料
型號(hào)： 28F640J5
廠(chǎng)商： Intel Corp.
英文描述： 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器)
中文描述： 5伏特英特爾StrataFlash存儲(chǔ)器（5V的6400位英特爾的StrataFlash閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 41/53頁(yè)
文件大?。?/td> 272K
代理商： 28F640J5
E
damping
overshoots and undershoots. Transceivers or
buffers with balanced- or light-drive outputs also
reduce overshoots and undershoots by diminishing
output-drive
currents.
buffer/transceiver interface design to flash, devices
with internal output-damping resistors or reduced-
drive outputs should be considered to minimize
overshoots
and
undershoots.
information, please refer to AP-647, 5 Volt Intel
StrataFlash
Memory
292205).
28F320J5/28F640J5
41
PRELIMINARY
resistors
help
reduce
unnecessary
When
selecting
a
For
additional
Design
Guide
(order
5.5
V
CC
, V
PEN
, RP# Transitions
Block erase, program, and lock-bit configuration are
not guaranteed if V
PEN
or V
CC
falls outside of the
specified operating ranges, or RP#
≠
V
IH
or V
HH
. If
RP# transitions to V
IL
during block erase, program,
or lock-bit configuration, STS (in default mode) will
remain low for a maximum time of t
PLPH
+ t
PHRH
until the reset operation is complete. Then, the
operation will abort and the device will enter
reset/power-down mode. The aborted operation
may
leave
data
partially
programming, or partially altered after an erase or
lock-bit configuration. Therefore, block erase and
lock-bit configuration commands must be repeated
after normal operation is restored. Device power-off
or RP# = V
IL
clears the status register.
corrupted
after
The CUI latches commands issued by system
software and is not altered by V
PEN
, CE
0
, CE
1
, or
CE
2
transitions, or WSM actions. Its state is read
array mode upon power-up, after exit from
reset/power-down mode, or after V
CC
transitions
below V
LKO
. V
CC
must be kept at or above V
PEN
during V
CC
transitions.
After block erase, program, or lock-bit configuration,
even after V
PEN
transitions down to V
PENLK
, the CUI
must be placed in read array mode via the Read
Array command if subsequent access to the
memory array is desired. V
PEN
must be kept at or
below V
CC
during V
PEN
transitions.
5.6
Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, programming, or lock-bit
configuration during power transitions. Internal
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PEN
is
active. Since WE# must be low and the device
enabled (see Table 2,
Chip Enable Truth Table
) for
a command write, driving WE# to V
IH
or disabling
the device will inhibit writes. The CUI’s two-step
command sequence architecture provides added
protection against data alteration.
Keeping V
PEN
below V
PENLK
prevents inadvertent
data alteration. In-system block lock and unlock
capability protects the device against inadvertent
programming. The device is disabled while RP# =
V
IL
regardless of its control inputs.
5.7
Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
相關(guān)PDF資料
PDF描述
28F400B3 SMART 3 ADVANCED BOOT BLOCK WORD-WIDE
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28F400BV-TB 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F640L18 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:StrataFlash Wireless Memory
28F640L30 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30)
28F640P3 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
28F640W30 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
28F650 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip
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