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參數(shù)資料
| 型號(hào)： | 28F008S5 |
| 英文描述： | Evaluation Kit/Evaluation System for the MAX5946A, MAX5946L |
| 中文描述： | 字節(jié)寬的SMART 5 FlashFile Memory系列4。 8。及16兆比特 |
| 文件頁(yè)數(shù)： | 4/44頁(yè) |
| 文件大?。?/td> | 496K |
| 代理商： | 28F008S5 |
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28F400BL-T/B, 28F004BL-T/B
The
Status Register (SR)
indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Maximum Access Time of
150 ns (t
ACC
)
is achieved
over the commercial temperature range (0
§
C to
a
70
§
C), V
CC
supply voltage range (3.0V to 3.6V,
4.5V to 5.5V) and 50 pF output load.
I
pp
Program current is 40 mA for x16 operation
and 30 mA for x8 operation. I
PP
Erase current is
30 mA maximum. V
PP
erase and programming
voltage is 11.4V to 12.6V (V
PP
e
12V
g
5%) un-
der all operating conditions.
Typical I
CC
Active Current of 15 mA
is achieved
for the x16 products and the x8 products.
The 4-Mbit flash family is also designed with an Au-
tomatic Power Savings (APS) feature to minimize
system battery current drain and allow for very low
power designs. Once the device is accessed to read
the array data, APS mode will immediately put the
memory in static mode of operation where I
CC
active
current is typically 0.8 mA until the next read is initia-
ted.
When the
CE
Y
and
RP
Y
pins are at V
CC
and the
BYTE
Y
pin (28F400BX-L-only) is at either V
CC
or
GND the
CMOS Standby
mode is enabled where
I
CC
is typically
45
m
A.
A
Deep Power-Down Mode
is enabled when the
PWD pin is at ground minimizing power consumption
and providing write protection during power-up con-
ditions.
I
CC
current
during deep power-down mode
is
0.20
m
A typical.
An initial maximum access time
or Reset Time of 600 ns is required from RP
Y
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 1
m
s until
writes to the Command User Interface are recog-
nized. When RP
Y
is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature pre-
vents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP
Y
to reset the memory to nor-
mal read mode upon activation of the Reset pin.
When the CPU enters reset mode, it expects to read
the contents of a memory location. Furthermore,
with on-chip program/erase automation in the
4-Mbit family and the RP
Y
functionality for data pro-
tection, when the CPU is reset and even if a program
or erase command is issued, the device will not rec-
ognize any operation until RP
Y
returns to its normal
state.
For the 2SF400BL, Byte-wide or Word-wide In-
put/Output Control
is possible by controlling the
BYTE
Y
pin. When the BYTE
Y
pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ
[
0:7
]
. During the byte-
wide mode, DQ
[
8:14
]
are tri-stated and DQ15/A
b
1
becomes the lowest order address pin. When the
BYTE
Y
pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ
[
0:15
]
.
1.3 Applications
The 4-Mbit low power boot block flash memory fami-
ly combines high density, very low power, high per-
formance, cost-effective flash memories with block-
ing and hardware protection capabilities. Its flexibility
and versatility will reduce costs throughout the prod-
uct life cycle. Flash memory is ideal for Just-In-Time
production flow, reducing system inventory and
costs, and eliminating component handling during
the production phase. During the product life cycle,
when code updates or feature enhancements be-
come necessary, flash memory will reduce the up-
date costs by allowing either a user-performed code
change via floppy disk or a remote code change via
a serial link. The 4-Mbit flash family provides full
function, blocked flash memories suitable for a wide
range of applications. These applications include
Extended PC BIOS and ROM-able
applications
storage,
Handy Digital Cellular Phone
program
and data storage and various other low power em-
bedded applications where both program and data
storage are required.
Portable systems such as Notebook/Palmtop com-
puters, are ideal applications for the 4-Mbit low pow-
er flash products. Portable and handheld personal
computer applications are becoming more complex
with the addition of power management software to
take advantage of the latest microprocessor tech-
nology, the availability of ROM-based application
software, pen tablet code for electronic hand writing,
and diagnostic code. Figure 1 shows an example of
a 28F400BL-T application.
This increase in software sophistication augments
the probability that a code update will be required
after the Notebook is shipped. The 4-Mbit flash
products provide an inexpensive update solution for
the notebook and handheld personal computers
while extending their product lifetime. Furthermore,
the 4-Mbit flash products’ deep power-down mode
provides added flexibility for these battery-operated
portable designs which require operation at very low
power levels.
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F008SC | 12V PWM Controller with Hot-Swap |
| 28F016S5 | 12V/5V Input Buck PWM Controller |
| 28F200BL-B | 2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F200BL-T | 5V/3.3V or Adjustable, Low-Dropout, Low-IQ, 500mA Linear Regulators |
| 28F200BV-B | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F008SA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:8 MBIT (1 MBIT x 8) FLASH MEMORY |
| 28F008SA-L | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:8 MBIT (1 MBIT x 8) FLASH MEMORY |
| 28F008SAT-ZW | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F008SC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4. 8. AND 16 MBIT |
| 28F010 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1024K (128K x 8) CMOS FLASH MEMORY |
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