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參數(shù)資料
| 型號： | 28F001BN-B |
| 英文描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 1兆位（128K的× 8）引導(dǎo)塊閃存 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 496K |
| 代理商： | 28F001BN-B |
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28F400BL-T/B, 28F004BL-T/B
1.6 Pin Descriptions for x8 28F004BL
Symbol
Type
Name and Function
A
0
–A
18
I
ADDRESS INPUTS
for memory addresses. Addresses are internally latched during
a write cycle.
A
9
I
ADDRESS INPUT:
When A
9
is at 12V the signature mode is accessed. During this
mode A
0
decodes between the manufacturer and device ID’s.
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE
Y
and WE
Y
cycle
during a program command. Inputs commands to the command user interface
when CE
Y
and WE
Y
are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
DQ
0
–DQ
7
I/O
CE
Y
I
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE
Y
is active low; CE
Y
high deselects the memory device and
reduces power consumption to standby levels.
RP
Y
I
RESET/DEEP POWER-DOWN:
Provides Three-State control. Puts the device in
deep power-down mode. Locks the Boot Block from program/erase.
When RP
Y
is at logic high level and equals 4.1V maximum the Boot Block is locked
and cannot be programmed or erased.
When RP
Y
e
11.4V minimum the Boot Block is unlocked and can be programmed
or erased.
When RP
Y
is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP
Y
transitions from logic low to logic high, the flash memory
enters the read-array mode.
OE
Y
I
OUTPUT ENABLE:
Gates the device’s outputs through the data buffers during a
read cycle. OE
Y
is active low.
WE
Y
I
WRITE ENABLE:
Controls writes to the Command Register and array blocks. WE
Y
is active low. Addresses and data are latched on the rising edge of the WE
Y
pulse.
V
PP
PROGRAM/ERASE POWER SUPPLY:
For erasing memory array blocks or
programming data in each block.
Note:
V
PP
k
V
PPLMAX
memory contents cannot be altered.
V
CC
DEVICE POWER SUPPLY (3.3V
g
0.3V, 5V
g
10%)
GND
GROUND:
For all internal circuitry.
NC
NO CONNECT:
Pin may be driven or left floating.
DU
DON’T USE PIN:
Pin should not be connected to anything.
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F001BN-T | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F001BX-B | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F002BL-B | 2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F002BL-T | 2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F002BV-T | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F001BN-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F001BX-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F001BX-T | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F001BX-T/28F001BX-B/28F001BN-T/BN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B |
| 28F001BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/B |
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