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參數(shù)資料
| 型號： | 27384A |
| 英文描述： | ±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up Circuitry |
| 中文描述： | 增加關于Am29BDD160G時鐘速度和更快的初步突發(fā)存取 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 27384A |
2
Increased Clock Speeds and Faster Initial Burst Access
December 12, 2002
BURST INITIAL ACCESS DELAY CONTROL
(BURST CONTROL CONFIGURATION)
Design modifications have decreased the Burst Initial
Access Delay by one clock cycle for all control register
configuration values and for frequencies up to 66 MHz.
Configuration Registers CR13 through CR10 deter-
mine the Burst Initial Access Delay. The Burst Initial
Access Delay is defined as the number of CLK cycles
that must elapse from the first valid clock edge after
ADV# assertion (or the rising edge of ADV#) until the
first valid CLK edge when the data is valid. Figure 1
and Table 1 are valid for the majority of applications,
and have the following operating conditions:
1.
Burst initial access starts with the first CLK rising
edge after ADV# assertion.
2.
Configuration Register 6 is set to 1 (CR[6] = 1).
Burst starts and data outputs on rising CLK edge.
For a complete discussion of this and other operating
conditions see the Am29BDD160G datasheet (Publi-
cation# 24960
Rev: C or later).
For example, Revision 4 control register setting CR[13-
10] = 0010 results in a Burst Initial Access Delay of five
clock cycles; while Revision 4a the same control regis-
ter setting results in a Burst Initial Access Delay with
four clock cycles.
.
Notes:
1. Burst access process starts when rising CLK edge after ADV# assertion.
2. Configuration register 6 is set to 1 (RC[6] = 1). Burst starts and data outputs on Rising CLK edge.
Figure 1.
Burst Initial Access Delay Control
Table 1.
Burst Initial Access Delay Control
Configuration Register Setting
Burst Initial Access Delay
(CLK cycles)
CR13
CR12
CR11
CR10
Rev. 4
Rev. 4a
0
0
0
0
3
2
0
0
0
1
4
3
0
0
1
0
5
4
0
0
1
1
6
5
0
1
0
0
7
6
0
1
0
1
8
7
0
1
1
0
9
8
0
1
1
1
10
9
Burst Initial Access Delay
1
3
2
CLK
ADV#
A18-A0
DQ31-DQ0
Valid
3 CLK cycles
Burst Initial Access Delay
D0
D1
D2
D3
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 273-8505-000 | 制造商:ITT Interconnect Solutions 功能描述:273-8505-000 / 273-8505-000 / TRANSPORTATION |
| 273-8506-001 | 制造商:ITT Interconnect Solutions 功能描述:BAYONET COMPONENT - Bulk |
| 273-8506-005 | 制造商:ITT Interconnect Solutions 功能描述:273-8506-005 - Bulk 制造商:ITT Interconnect Solutions 功能描述:CIRCULAR CABLE SEAL 1.4MM TO 2MM 制造商:ITT Interconnect Solutions 功能描述:CIRCULAR CABLE SEAL, 1.4MM TO 2MM; Series:APD / DIN 72585; For Use With:APD / DIN 72585 Circular Connectors; Cable Diameter Max:2mm; Accessory Type:Individual Wire Seal; Connector Type:Circular Industrial |
| 273-8506-006 | 制造商:ITT Interconnect Solutions 功能描述:273-8506-006 - Bulk 制造商:ITT Interconnect Solutions 功能描述:CIRCULAR CABLE SEAL, 2MM TO 2.9MM; Series:APD / DIN 72585; For Use With:APD / DIN 72585 Circular Connectors; Cable Diameter Max:2.9mm; Accessory Type:Individual Wire Seal; Connector Type:Circular Industrial |
| 273-8506-007 | 功能描述:APD WIRE HOLE FILRS WHT LOOSE RoHS:是 類別:連接器，互連式 >> 圓形 - 配件 系列:APD 4 路 其它有關文件:Plating Finishes 標準包裝:1 系列:- 附件類型:應力消除 適用于相關產(chǎn)品:MIL-DTL-38999 系列 III、IV 外殼尺寸 - 插件:23 材質:鋁，鍍鎳鎘 特點:自鎖定 顏色:橄欖色 配用:AD38999/26WH55SN-ND - CONN PLUG 55POS STRAIGHT W/SCKTAD38999/26WH55SD-ND - CONN PLUG 55POS STRAIGHT W/SCKTAD38999/26WH55SC-ND - CONN PLUG 55POS STRAIGHT W/SCKTAD38999/26WH55SA-ND - CONN PLUG 55POS STRAIGHT W/SCKTAD38999/26WH55PN-ND - CONN PLUG 55POS STRAIGHT W/PINSAD38999/26WH55PC-ND - CONN PLUG 55POS STRAIGHT W/PINSAD38999/26WH55PA-ND - CONN PLUG 55POS STRAIGHT W/PINSAD38999/26WH55JA-ND - CONN PLUG 55POS STRAIGHT W/SCKTAD38999/26WH55HA-ND - CONN PLUG 55POS STRAIGHT W/PINSAD38999/26WH53SN-ND - CONN PLUG 53POS STRAIGHT W/SCKT更多... 其它名稱:A8504938S23W-NDAPC1389M85049/38S23W |
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