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| 型號： | 27384A |
| 英文描述： | ±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up Circuitry |
| 中文描述： | 增加關(guān)于Am29BDD160G時鐘速度和更快的初步突發(fā)存取 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 81K |
| 代理商： | 27384A |
Publication# 27384
Issue Date:
December 12, 2002
Rev: A Amendment/
0
1
Increased Clock Speeds and Faster Initial Burst Access
Modification to Burst Initial Access Delay Control and CFI Device Geometry Definition–
Revision 4a versus Revisions 4 and Earlier
Application Note
INTRODUCTION
This Application Note discusses design improvements
to the Am29BDD160G. Technology and application
developers are increasingly requiring Flash memory
with higher clock speeds and faster access times. This
is particularly true for the automotive market in anti-lock
braking, engine control, and transmission control appli-
cations. One of the factors affecting system
performance is the interface between the Flash mem-
ory and the microprocessor. Flash memory in burst
mode (synchronous) requires a longer access time for
the initial access than subsequent accesses (as fast as
one clock cycle at 66 MHz). Flash burst initial access
delay is therefore an important factor influencing sys-
tem performance.
AMD is the world leader in Flash memory design, de-
velopment and production, and is committed to
continuous improvement of Flash memory capability.
The Am29BDD160G 16 megabit Flash memory is a
prime example of how this commitment is driving de-
sign modifications. Improvements to the
Am29BDD160G have resulted in significantly de-
creased the burst initial access delay. The number of
wait states associated with the burst initial access in
Revision 4a (versus all previous revisions) has been
decreased by one state across all frequencies. The
Am29BDD160G now provides for a 66 MHz operation
with a burst initial access time of five clock cycles and
subsequent burst access time of one clock cycle (also
known as 5-1-1-1… at 56 MHz and 66 MHz).
Design improvements require changes to both the sili-
con revision level (incremented from 4 to 4a) and the
Am29BDD160G datasheet revision level (incremented
from B to C). There are three areas of discussion:
■
Initial Access Delay Control
User Configurable Control Register determines the ini-
tial access delay in burst mode i.e., Initial Access Delay
Control (Burst Control Configuration). Allows for proper
configuration of the Flash memory to match the micro-
processor interface.
■
CFI Device Geometry Definition
Fixed configuration information in Common Flash
Memory Interface i.e., CFI Device Geometry Definition
containing details about memory size, word–size, and
erase block configuration.
■
Summary of Silicon Revision 4 and 4a Differ-
ences
Discussion of differences between silicon revision 4
from 4a with respect to external attributes (such as part
number, part marking) and internally through interroga-
tion of Flash configuration registers (software). This
third section also discusses issues that should be con-
sidered when different revision level devices are used.
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