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參數(shù)資料
| 型號： | 2501NZ |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual N-Channel 2.5V Specified PowerTrench MOSFET |
| 中文描述： | 雙N溝道MOSFET的為2.5V指定的PowerTrench |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 117K |
| 代理商： | 2501NZ |
FDW2501NZ Rev
E1
(W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
BV
DSS
T
J
Coefficient
I
DSS
Zero Gate Voltage Drain Current
I
GSSF
Gate–Body Leakage, Forward
I
GSSR
Gate–Body Leakage, Reverse
V
GS
= 0 V, I
D
= 250
μ
A
20
V
Breakdown Voltage Temperature
I
D
= 250
μ
A, Referenced to 25
°
C
14
mV/
°
C
V
DS
= 16 V,
V
GS
= 12 V,
V
GS
= –12 V,
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
1
10
–10
μ
A
μ
A
μ
A
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
GS(th)
T
J
Temperature Coefficient
R
DS(on)
Static Drain–Source
On–Resistance
(Note 2)
V
DS
= V
GS
, I
D
= 250
μ
A
I
D
= 250
μ
A, Referenced to 25
°
C
V
GS
= 4.5 V,
V
GS
= 2.5 V,
V
GS
= 4.5 V, I
D
= 5.5 A, T
J
=125
°
C
V
GS
= 4.5 V,
V
DS
= 5 V,
0.6
1.0
1.5
V
Gate Threshold Voltage
–3
mV/
°
C
I
D
= 5.5 A
I
D
= 5 A
14
19
19
30
18
25
29
m
A
S
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
V
DS
= 5 V
I
D
= 5.5 A
30
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
1286
305
161
pF
pF
pF
V
DS
= 10 V,
f = 1.0 MHz
V
GS
= 0 V,
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
10
14
25
8
12
2.6
3
20
25
40
16
17
ns
ns
ns
ns
nC
nC
nC
V
DD
= 10 V,
V
GS
= 4.5 V,
I
D
= 1 A,
R
GEN
= 6
V
DS
= 10 V,
V
GS
= 4.5 V
I
D
= 5.5 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
1.0
1.2
A
V
V
GS
= 0 V,
I
S
= 1.0 A
(Note 2)
0.7
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) R
θ
JA
is 100
°
C/W (steady state) when mounted on a 1 inch2 copper pad on FR-4.
b) R
θ
JA
is 125
°
C/W (steady state) when mounted on a minimum copper pad on FR-4.
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
3.
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
F
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