
List of Tables
v
24267A/0—December 2000
Preliminary Information
List of Tables
Table 1.
Basic Set of AMD PowerNow! Technology
Operational Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Enhanced Power Management Register (EPMR) Definition . . 4
EPM 16-Byte I/O Block Definition . . . . . . . . . . . . . . . . . . . . . . . . 6
Processor-to-Bus Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Divisor and Voltage ID Control (BVC) Definition. . . . . . . 11
VID [4:0] Input-to-Output Voltage Codes (Typical for
DC/DC Regulators). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Regulator Solution Using a Subset of CPU VID Outputs . . . . 13
Alternative Components for AMD PowerNow! Technology
Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supported Voltages and Operating Frequencies for Low-Power
AMD-K6-2E+ Processors Enabled with
AMD PowerNow! Technology . . . . . . . . . . . . . . . . . . . . . . . . . 23
Supported Voltages and Operating Frequencies for Low-Power
AMD-K6-IIIE+ Processors Enabled with
AMD PowerNow! Technology . . . . . . . . . . . . . . . . . . . . . . . . . 23
AMD PowerNow! Technology Descriptor Table . . . . . . . . . . 31
Pins Added for AMD PowerNow! Technology. . . . . . . . . . . . 33
CPGA Pin Designations by Functional Grouping . . . . . . . . . . .34
CPGA Pin Designations for No Connect, Reserved,
Power, and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
OBGA Pin Designations by Functional Grouping. . . . . . . . . . .36
OBGA Pin Designations for No Connect, Reserved,
Power, and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.