
Dynamic Core Frequency and Core Voltage Control
13
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
Table 7.
Table 6.
VID [4:0] Input-to-Output Voltage Codes (Typical for DC/DC Regulators)
VID Inputs
Output
Voltage
VID Inputs
Output
Voltage
D[4]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D[4]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.00 V
1.95 V
1.90 V
1.85 V
1.80 V
1.75 V
1.70 V
1.65 V
1.60 V
1.55 V
1.50 V
1.45 V
1.40 V
1.35 V
1.30 V
Shutdown
1
1.275 V
1.250 V
1.225 V
1.200 V
1.175 V
1.150 V
1.125 V
1.100 V
1.075 V
1.050 V
1.025 V
1.000 V
0.975 V
0.950 V
0.925 V
Shutdown
1
Notes:
1.
If the voltage regulator is to be powered when the processor is to be powered off (for example, during Suspend to RAM), it is necessary
to assert the regulator’s shutdown pin to power off the processor.
Regulator Solution Using a Subset of CPU VID Outputs
Max1711 Regulator
D[4:0] Inputs
Connection to CPU VID
Outputs
CPU VID[4:0]
Outputs
1
0x0x0
Notes:
1.
2. Regulator D[4] and D[0] are tied to GND.
3. Assumes a resistor divide circuit is used with the regulator to support a 2.1-V core voltage.
4. CPU VID[4], VID[2], and VID[0] are connected to the regulator through external logic.
CPU VID[3] and VID[1] are each treated as an NC (no-connect) and represented by “x”.
Regulator D[4:0]
Inputs
2
00000
Voltage Selected
3
D[4]
GND
2.00 V
D[3]
CPU VID[4]
4
CPU VID[2]
4
CPU VID[0]
4
GND
0x0x1
00010
1.90 V
D[2]
0x1x0
00100
1.80 V
D[1]
0x1x1
00110
1.70 V
D[0]
1x0x0
1x0x1
1x1x0
1x1x1
01000
01010
01100
01110
1.60 V
1.50 V
1.40 V
1.30 V