參數(shù)資料
型號(hào)： 23913A
英文描述： Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF)
中文描述： 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式）
文件頁數(shù)： 55/98頁
文件大?。?/td> 1365K
代理商： 23913A
Model 9 Registers
43
23913A/0—November 2000
Embedded AMD-K6 Processors BIOS Design Guide
Preliminary Information
Figure 15. L2 Tag Information (AMD-K6
-III
Processor)—EAX
LRU (Least Recently
Used) Field
For the 4-way set associative L2 cache, each way has a 2-bit LRU
field for each sector. Values for the LRU field are 00b, 01b, 10b,
and 11b, where 00b indicates that the sector is “most recently
used,” and 11b indicates that the sector is “l(fā)east recently used”
(see Figure 16). EAX[7:6] indicate LRU information for Way 0,
EAX[5:4] for Way 1, EAX[3:2]
for
Way 2, and EAX[1:0]
for
Way 3.
Figure 16. LRU Byte
Writing to L2 Tag of
AMD-K6
-III
Processor
When writing to the L2 tag of the AMD-K6-III processor, special
consideration must be given to the least significant bit of the
Tag field of the EAX register— EAX[15]. The length of the L2
tag required to support the 256-Kbyte L2 cache on the
AMD-K6-III processor is 16 bits, which corresponds to bits 31:16
of the EAX register. However, the AMD-K6-III processor
provides a total of 17 bits for storing the L2 tag—that is, 16 bits
for the tag (EAX[31:16]), plus an additional bit for internal
purposes (EAX[15]). During normal operation, the AMD-K6-III
processor ensures that this additional bit (bit 15) always
corresponds to the set in which the tag resides. Note that bits
C
M
D
Reserved
Description
Tag data read or written
Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10
Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8
LRU
Two bits of LRU for each way
0
Tag
15
31
14
12
10 9
7
8
11
LRU
Line0ST
Line1ST
Symbol
Tag
Bit
31-15
7-0
7
6
5
4
3
2
1
0
Way 2
LRU Values
00b Most Recently Used
01b Used More Recently Than 10b, But Less Recently Than 00b
10b Used More Recently Than 11b, But Less Recently Than 01b
11b Least Recently Used
Way 3
Way 0
Way 1
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