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| 型號： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設計指南應用筆記？ 1.33MB（PDF格式） |
| 文件頁數(shù)： | 21/98頁 |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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States after RESET and INIT
9
23913A/0—November 2000
Embedded AMD-K6 Processors BIOS Design Guide
Preliminary Information
Processor State after INIT
The assertion of INIT causes the processor to empty its
pipelines, initialize most of its internal state, and branch to
address FFFF_FFF0h—the same instruction execution starting
point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
SMM base, MSRs, and the CD and NW bits of the CR0 register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from protected mode back to real mode.
Table 4.
AMD-K6-2E+ (Model D), AMD-K6
-III
(Model 9), and
AMD-K6-
III
E+ Processors (Model D) State after RESET
Register
RESET State
0000_05MSh
1
EDX
Notes:
1.
2. Because EFER[4] equals 0 after RESET, the L2 cache is enabled by default after RESET.
3. “B” represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is equal to the value of the
BF[2:0] signals sampled during the falling transition of RESET.
4. Supported on low-power versions only of Model D processors.
“M” represents the Model and “S” represents the Stepping.
EFER
2
L2AAR
PFIR
0000_0000_0000_0002h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_00SBh
1,3
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
PSOR
STAR
UWCCR
WHCR
EPMR
4
0000_0000_0000_0000h
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