
4
3.0 Volt-only Burst Mode Technology Background
Read Operation
The Am29BL162C will power-up in an “asynchronous read” operating mode. In this mode,
the device operates like a conventional Flash device (Am29LVxxx) and supports only
asynchronous, random reads, not synchronous burst reads. To support burst reads, the
Am29BL162C must be put into the bust mode by writing the Burst Enable command
sequence. To exit the burst mode, the device must be given the Burst Disable command
sequence.
Random Read Operation
In the asynchronous mode the Am29BL162C has two control functions which are used to
obtain data at the outputs. CE# should be used for device selection. OE# is the output control
and should be used to gate data to the output pins after the device is selected.
Burst Mode Read Operation
In order to operate in burst mode, three additional control pins have been added. These
control pins allow easy interfacing to a wide range of microprocessors with minimal glue
logic to achieve high performance burst read capability. These additional pins are as follows:
Load Burst Address (LBA#), Burst Address Advance (BAA#), and Clock (CLK).
The burst mode read operation is a synchronous operation tied to the rising edge of the clock.
The microprocessor or microcontroller supplies only the initial address. All subsequent
addresses are automatically generated by the device at the rising edge of subsequent clock
cycles by asserting the BAA# signal.
The burst read cycle consists of an address phase and a corresponding data phase. During the
address phase, the Load Burst Address (LBA#) pin must be held low for one clock period. At
the rising edge of CLK, the starting burst address is loaded into the internal burst address
counter.
During the data phase, the first burst data is available after the initial access time (t
ACC
) from
the rising edge of CLK. For subsequent burst data, an active Burst Address Advance (BAA#)
and the rising edge of the CLK will increment the counter and supply the remaining data in
the appropriate sequence in the specified burst access time (t
BACC
). The stream of data will be
provided as long as the BAA# pin is asserted.
The timing diagram in Figure 2 demonstrates this burst mode operation.