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參數(shù)資料
| 型號： | 22152 |
| 元件分類： | SRAM |
| 英文描述： | 64K Nonvolatile SRAM |
| 中文描述： | 使用AMD的設(shè)備運(yùn)行狀態(tài)位 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 127K |
| 代理商： | 22152 |
4
Using the Operation Status Bits in AMD Devices
July 24, 2002
S U P P L E M E N T
tasks after issuing the erase command. The RY/
BY# pin will interrupt the microprocessor when
the operation is complete. Note that some AMD
devices do not offer the RY/BY# pin, in which
case the host system will have to rely on polling
the DQ6 or DQ7 Status Bits.
4.
Checking if a Sector is in the Erase Suspend
Mode:
To determine if a particular sector is in
the
Erase Suspend Mode the system will have to poll
both the DQ2 and DQ6 Operation Status Bits to-
gether. Note: The Am29F010, Am29F100 Bulk
Erase devices do not support the Erase Suspend
feature.
Polling DQ2 & DQ6:
Once a sector is in the Erase Suspend Mode
DQ2 toggles but DQ6 does not
,
with successive
reads from any location within the suspended
sector. Once in the Erase Suspend Mode, the
device can perform a Read or Program opera-
tion in a non-erase suspended sector. When an
Erase Resume command is issued the sector
resumes the Erase operation and
both
DQ2 and
DQ6 will continue to toggle. When the Erase op-
eration is complete, both DQ2 and DQ6 will stop
toggling. Note that some AMD devices do not
offer the DQ2 Operation Status Bit, in which
case this application is not feasible. Refer to Fig-
ure 6 for the appropriate polling sequence.
5.
Ensuring that the Program/Erase operation has
completed successfully:
The DQ5 Status Bit indi-
cates whether program or erase has exceeded
internally specified pulse count limits. This a failure
condition which signifies that the Program/Erase
operation was not completed successfully. There-
fore when polling for Program or Erase completion,
DQ5 must also be polled in conjunction with the
other Status Bits.
Polling DQ5:
If a Program or Erase operation is not successful
the DQ5 Status Bit will be set to a
“
1
”
. Under this
condition, DQ7 will not output valid data and
DQ6 will continue to toggle. To acknowledge this
condition and return the device to the Read
mode the system must issue a Reset command.
Refer to Figures 3, 4, 5 and 6 for the appropriate
polling sequence.
6.
Checking if the Sector Erase time-out window is
open:
All Am29xxxxx Flash devices support the
erasing of multiple sectors after issuing a single
Sector Erase command sequence. The sectors
may be selected for Erase in any order: For exam-
ple Sector 9 first and Sector 1 next, etc. A Sector
Erase is a six bus cycle operation (see datasheet).
There are two unlock write cycles followed by a set-
up cycle. Two more unlock cycles are then followed
by the actual Sector Erase command cycle (sector
address + Sector Erase command: 30h). After the
Sector Erase command cycle is written (6th bus cy-
cle), the Sector Erase time-out window of 50 μs
begins. The next Sector Erase command cycle must
be written before this 50 μs time-out period expires.
Every time the system writes an additional Sector
Erase command (30h), the 50 μs time-out window is
reset and another Sector Erase command cycle may
be written within 50 μs. The following example illus-
trates the sequence to be implemented to erase 3
sectors.
6th bus cycle:
Address of the 1st sector to be erased +
30h (Sector Erase command)
50 μs time-out begins
7th bus cycle:
Address of the 2nd sector to be erased +
30h (Sector Erase command)
Time-out window is reset and
50 μs time-out begins again
8th bus cycle:
Address of the 3rd sector to be erased +
30h (Sector Erase command)
Sector Erase operation begins
after 50 μs.
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