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參數(shù)資料
| 型號： | 22152 |
| 元件分類： | SRAM |
| 英文描述： | 64K Nonvolatile SRAM |
| 中文描述： | 使用AMD的設(shè)備運行狀態(tài)位 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 127K |
| 代理商： | 22152 |
2
Using the Operation Status Bits in AMD Devices
July 24, 2002
S U P P L E M E N T
to the Status Register. The Flash device is now operat-
ing as a peripheral. By executing a read bus cycle to
the Flash device the Operation Status Bits are fetched
from the status register and presented on the data pins
(DQ0-DQ7). After a Program or Erase operation is
complete, the multiplexer switches the data pins back
to the memory array. The Flash device now reverts
back to operating as a memory.
Please note that Status Bits are valid after the WE# ris-
ing edge on the last command and any applicable
program/erase time-outs.
Figure 1.
Data Pins Multiplexed between the
Memory Array and Status Register
HOW CAN THE HOST SYSTEM ACCESS
THE OPERATION STATUS BITS
The Operation Status Bits may be accessed by a sim-
ple Read cycle. All Status Bits are valid after the rising
edge of the final WE# pulse in the Program/Erase com-
mand sequence. The microprocessor may (a)
continuously poll the Status Bits immediately after the Pro-
gram/Erase command sequence is written or (b)
periodically poll the Status Bits while performing other
tasks. The designer has the option to implement the ap-
propriate polling method depending on the specific
host system. For an example see Figure 2.
Figure 2.
Example of Am29F040 Program Operation
MEMORY ARRAY
STATUS REGISTERS
DQ0 - DQ7
OE#
CE#
Address
Pins
WE#
5555h
2AAAh
5555h
PA
PA
Program Command Sequence
Read Status Register
AAh
55h
A0h
PD
Status Register
Data Bus
Data Write Cycle (1)
Program Set Up
Command Cycle (1)
Command Unlock Cycles (2)
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