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參數(shù)資料
| 型號： | 21728 |
| 英文描述： | 4-Bit, Dual, Programmable Delay Line |
| 中文描述： | 接口的Am188EM的DSLAC？ / QSLAC？使用小型工業(yè)應用筆記？ 84.0KB（PDF格式） |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 84K |
| 代理商： | 21728 |
4
Interfacing the Am188
TM
EM Controller to the DSLAC
TM
/QSLAC
TM
Devices Using the SSI
data out to the DSLAC device is calculated as de-
scribed in the following paragraph.
The DSLAC device requirement is read directly from
the data sheet parameter #10 (t
IDS
- Input Data Setup
Time). This value is 30 ns for both the DSLAC and
QSLAC devices. Determining what the Am188EM mi-
crocontroller provides takes a little calculation. First,
decide what the minimum low period is for SCLK. This
is really determined by the DSLAC device, where the
minimum DCLK low period is determined by parameter
#3 (t
DCL
- Data Clock Low Pulse Width), which is 97 ns.
SDATA is guaranteed to be stable no more than 25 ns
after the falling edge of SCLK by parameter #78
(t
SLDV
- SCLK Low to Data Valid) for the slowest pro-
cessor (20 MHz). Subtracting 25 from 97 leaves 72 ns
worst-case setup time before the rising edge of DCLK.
The previous example assumes worst-case duty cycle
for DCLK. The fastest clock allowed has a period of
244 ns, but if the clock is not perfectly symmetric, either
the Low or High period can be as short as 97 ns rather
than one half of the clock rate (122 ns). In the case of
the Am188EM microcontroller this is probably over-de-
sign. Because SCLK’s frequency is related to one half
CLKOUTA, it should always be close to a 50% duty cy-
cle. In this case, the data setup time provided by the
Am188EM microcontroller is closer to 97 ns.
As the tables illustrate, there are generous margins
even in the worst case.
In the case of the data hold time in Table 2, there is no
specification given in the Am188EM microcontroller
data sheet for how quickly SDATA can change after the
clock goes Low. It is assumed that the worst case is
that SDATA will instantaneously change as soon as
SCLK goes Low. This means that the hold time pro-
vided by the Am188EM microcontroller is the same as
the minimum SCLK High period specified by the
DSLAC device as 97 ns.
The CS setup and hold time times are given for the
case where SDEN is driven from inverters as dis-
cussed above. Even though SDEN is driven by the SSI
interface, it is still controlled by software by writing a
one or zero to the DE0 or DE1 bits in the synchronous
serial control (SSC) register. Because they are con-
trolled by software, the actual delays will be much
longer than specified. The same will hold true if PIOs
are used to drive the SLAC device chip selects.
Table 3 gives the usable options for each of the avail-
able speed grades and the resultant data transfer rate.
To achieve the maximum DCLK rate of 4 MHz, the
Am188EM microcontroller’s internal frequency must be
8, 16, or 32 MHz (÷2, 4, or 8).
Table 2.
Microprocessor Output (Data Write)
Table 3.
Microprocessor Input (Data Read)
SOFTWARE CONSIDERATIONS
The basics of using the SSI port from software can be
illustrated with two subroutines; the first subroutine
writes a byte to the SLAC device and the second reads
a single byte. These two subroutines, along with initial-
ization, form the core of the necessary drivers.
The SSI port appears as five registers in the Am188EM
microcontroller’s peripheral control block. This
256-byte block can be located in either memory or I/O
space at the location pointed to by the Peripheral Con-
trol Block Relocation Register. Because the base loca-
tion of the block can be moved, the location of
individual registers is specified as an offset from the
Peripheral Control Block Relocation Register rather
than an absolute address. The PIO ports and control
registers are also located in this block of addresses. At
reset, the block is located at 0FF00h in the I/O space.
DSLAC Device Requires
(ns, min)
30
30
70
0
Am188EM Microcontroller
Provides (ns, min)
72
97
219
122
Comments
OK
OK
OK
OK
Data setup time
Data hold time
CS setup time
CS hold time
Am188EM
Microcontroller Requires
(ns, min)
10
3
DSLAC Device Provides
(ns, min)
47
97
Comments
OK
OK
Data setup time
Data hold time
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