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參數(shù)資料
| 型號： | 21582 |
| 英文描述： | Gigabit Ethernet Physical Layer GigaPHY-SD Device Design Considerations? 49.2KB (PDF) |
| 中文描述： | 千兆以太網(wǎng)物理層GigaPHY - SD設備設計考慮？ 49.2KB（PDF格式） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 49K |
| 代理商： | 21582 |
6
Design Considerations for the Am79761 Gigabit Ethernet Physical Layer GigaPHY-SD Device
Figure 8.
5 V to 3.3 V Conversion using a Linear Regulator
A DC/DC Converter that is appropriate for powering the
GigaPHY-SD device is the Linear Technology, LT1256
1.5A part. The DC/DC converter circuit is not shown
here since excellent application notes are provided by
the manufacturer.
BYPASSING
The method in which bypass capacitors are used to fil-
ter the power supply to the GigaPHY-SD device has a
significant impact upon signal quality. First, it is manda-
tory that the design include a power plane for VSS
(Ground) which is at least 1 oz. copper. Secondly, a
similar power plane for VDD (3.3 V) is strongly recom-
mended. To reduce inductance, vias used to connect to
these planes should not include thermal cut-outs simi-
lar to those found on VDD/VSS connections to through-
hole components. It is strongly suggested that each
power and ground pin be supplied from their own vias.
Bypass capacitors are more effective when located on
the same side of the PCB as the GigaPHY-SD device.
Of course, the capacitors
must
possible to the VDD and VSS pins of the chips. Further-
more, it is recommended that the capacitor be located
be located as closely as
between the pin and the via to the plane. The preferred
method for the layout of the bypassing capacitors is
shown in Figure 9. Since AMD’s GigaPHY-SD device
has roughly constant power supply current, there is no
need for exotic bypassing methods (i.e., two capacitors
in parallel aimed at the switching frequency of the inter-
nal circuit). It is also recommended that the power and
ground planes remain intact rather than attempting to
steer current paths through sculpted planes. Most cus-
tomers who have tried to isolate the planes for the
transmitters and receivers usually produce more noise,
rather than reduce noise.
The GigaPHY-SD has internal PLLs which are powered
from separate supply pins usually called AVDD/AVSS
where the “A” denotes analog. These pins are particu-
larly sensitive to noise, so additional care must be
taken to filter out noise. It is recommended that AVDD
pass through a ferrite bead (i.e., TDK CB50-1206) to a
bypass capacitor (at least one 0.1
pin. The layout shown in Figure 9 indicates the pre-
ferred method for layout of this circuit.
μ
F) and the power
Figure 9.
Bypassing Layout Example
LT1086
CM-3.3
IN
ADJ
OUT
10
μ
F
10
μ
F
0.1
μ
F
5 V
3.3 V
21582B-8
DVSS
DVDD
AVDD
AVSS
GigaPHY_SD
0.1
μ
F
0805
0.1
μ
F
0805
Ferrite
TDK CB50
-1206
21582B-9
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