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| 型號： | 21582 |
| 英文描述： | Gigabit Ethernet Physical Layer GigaPHY-SD Device Design Considerations? 49.2KB (PDF) |
| 中文描述： | 千兆以太網(wǎng)物理層GigaPHY - SD設(shè)備設(shè)計(jì)考慮？ 49.2KB（PDF格式） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 49K |
| 代理商： | 21582 |
Design Considerations for the Am79761 Gigabit Ethernet Physical Layer GigaPHY-SD Device
5
Figure 6.
Termination Example: Preventing Oscillation
In the circuit shown in Figure 7, 47K
tors are added in parallel with the internal 3 K
This results in a 50-mV offset. The capacitor across
the inputs provides a low-impedance path to reduce
noise susceptibility.
external resis-
pair.
Figure 7.
Termination Example: Unused Inputs
POWER SUPPLY CONSIDERATIONS
Generating 3.3 V from a Linear Regulator
AMD’s Gigabit Ethernet PHYs operate with a 3.3 V
±
5% power supply. Although the migration to 3.3 V
logic power supplies is underway, many systems do
not have an available 3.3 V supply. The easiest, small-
est, and cheapest way to convert from a 5 V power
supply to a 3.3 V level is through the use of a linear
regulator. Converting from a +12 V supply to a 3.3 V
supply is more difficult due to the additional power dis-
sipation in the regulator that must be handled cor-
rectly. At 5 V
±
10%, the power dissipated in the
regulator is calculated as (5.25 V - 3.3 V)*IDD(max).
The advantage of a linear regulator is that it provides
a very quiet output that is isolated from the noise on
the 5 V supply. Since signal jitter is sensitive to power
supply noise, the clean outputs of the linear regulator
contribute to improved signal quality.
A readily available, multiple-sourced linear regulator
is the Linear Technology LT1086CM-3.3, which is a
fixed 3.3 V output voltage regulator that provides up to
1.5 A output current. This is more than adequate to
power the GigaPHY-SD device. A simple application
circuit is shown in Figure 8. Minimum values of input
and output capacitance are required to provide stabil-
ity to the regulator. Additional bypass capacitors must
be added for additional power supply filtering at the
pins of the chip. Similar linear regulators with different
current limits are the LT1117CST-3.3 (800 mA, SOT-
223) and the LT1586CM-3.3 (4A, TO-220), both from
Linear Technology.
Generating 3.3 V from a DC/DC Converter
The limitation of a linear regulator is that it is not effi-
cient, therefore, heat is generated. In applications
where excessive heat is not acceptable, a DC/DC Con-
verter may be used to convert either the 5 V or 12 V
supplies into a 3.3 V supply. The DC/DC converters
available for the current levels needed in this applica-
which reduces heat generation. However, the DC/DC
converters are more expensive, require more real es-
tate, require more components, are not trivial to use,
and add noise to the 3.3 V supply. The noise is a con-
cern since power supply noise will couple into the PLL
circuits and buffers of the transmitter and receiver,
thereby, increasing jitter generation in the transmitter
and reducing jitter tolerance in the receiver. If a DC/DC
converter is used, extra care should be taken to reduce
output noise.
RX
C1
R3
C2
R4
RX+
RX–
VDD VDD
R1
R2
+30 mV
–30 mV
R1=R4=97.6
, 1% R2=R3=102
, 1% for 50
impedance, [72 mV offset]
R1=R4=147
, 1% R2=R3=154
, 1% for 75
impedance, [76 mV offset]
C1=C2=0.01
μ
F
21582B-6
RX
C1
R2
VDD
R1
+50 mV
–50 mV
R1=R2=47K
, 5%
C1=0.01
μ
F
21582B-7
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