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參數資料
| 型號： | 21176 |
| 英文描述： | Designing 100BASE-TX? 86.8KB (PDF) System with the QFEX Family ? |
| 中文描述： | 設計100BASE - TX的？ 86.8KB（PDF格式）系統(tǒng)？與QFEX家庭 |
| 文件頁數： | 9/15頁 |
| 文件大?。?/td> | 86K |
| 代理商： | 21176 |
Designing 100BASE-TX Systems with the QFEX Family
9
Figure 8.
QFEXr Connection to MLT-3 and Magnetics Components for 100BASE-TX
GENERAL CIRCUIT DESIGN AND LAYOUT
GUIDELINES
High speed design is always a tricky issue, and it be-
comes critical to follow basic guidelines in order to en-
sure a clean design.
To optimize a design for the QFEXr device, designers
must follow basic rules in layout and placement, decou-
pling and isolation, clock and oscillator considerations,
general terminations, power supply filtering and plane
partitioning, and finally, EMI considerations. The com-
bination of these rules will contribute greatly to a proper
functioning 100-Mbps repeater system. Above all, sug-
gestions from PHY, transceiver and magnetics vendors
should be followed when designing a specific solution.
Parts Recommendations
Resistors should be 1% tolerance.
Capacitors:
— For low frequency and large value decoupling,
use electrolytic capacitors.
— For high frequency and small value decoupling,
use X7R and C0G capacitors.
I
I
I
Recommended ferrite beads are Fair Rite
274-3019-446.
Fully Shielded RJ-45 8-position jacks.
Placement and Layout
Placement and layout are the key components of board
design. Much care if given to performing these tasks
properly ensures a good design. Noise, ringing, trans-
mission lines, and other factors have to be controlled.
Data lines should have a controlled impedance and be
properly terminated, and power supply pins should be
protected by proper filtering techniques. All PC traces
should be treated as transmission lines with continuous
ground or power planes beneath each trace.
I
Placement of the QFEXr PHY device should be sym-
metrical with respect to the repeater device. This will
provide more equal trace length to each PHY and
counteract most timing/skew problems, especially with
synchronization of the clock to all clock-based compo-
nents. The QFEXr devices should also be close to the
repeater or buffers to minimize trace length and exces-
sive line ringing, due to high-speed data transfers.
Proper termination should be used.
When placing decoupling components, traces should be
kept as short as possible, especially for the transceiver
Note
: Required pullup/pulldown resistors and MLT-3 details are not shown. Consult MLT-3 vendor for recommendations.
FLS_CRS[3:0]
TX0+/–
RX0 +/–
SDI0 +/–
TX1+/–
RX1+/–
SDI1+/–
TX2+/–
RX2+/–
SDI2+/–
TX3+/–
RX3+/–
SDI3+/–
DIS_MLT3
LPBCK
TXD[3:0]
TX_ER[3:0]
TX_EN[3:0]
21
26, 25, 24, 23
75, 87, 6, 20
Repeater
QFEXr
70
DVDD
ENCIM
DISSCR
Port 0
Port 1
Port 2
Port 3
MLT-3
Array
TXO_0+/–
RXI_0+/–
TXO_1+/–
RXI_1+/–
TXO_2+/–
RXI_2+/–
TXO_3+/–
RXI_3+/–
M
R
CLK
25 MHz
OSC
LED[3:0]
72, 84, 95, 8
32, 31, 30, 29
93, 92, 91, 90
69
42, 44
40, 41
45, 47
50, 52
48, 49
53, 55
58, 60
56, 57
61, 63
66, 68
64, 65
34
33
37, 39
Shared
MII Interface
COL[3:0]
RXD[3:0]
RX_DV
RX_CLK
RX_ER
MDC
MDIO
CRS[3:0]
73, 85, 1, 15
74, 86, 2, 16
9, 10, 11, 12
17
18
19
98
97
TX_CLK
ENRCV[3:0]
89
76, 88, 7, 22
DVSS
21176B-8
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