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參數(shù)資料
| 型號(hào)： | 21176 |
| 英文描述： | Designing 100BASE-TX? 86.8KB (PDF) System with the QFEX Family ? |
| 中文描述： | 設(shè)計(jì)100BASE - TX的？ 86.8KB（PDF格式）系統(tǒng)？與QFEX家庭 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 86K |
| 代理商： | 21176 |
10
Designing 100BASE-TX Systems with the QFEX Family
interface. Short traces minimize noise interference.
These components, if using many transceivers, should
be placed symmetrically across the board to avoid un-
even parasitic loading. It is preferred to have decoupling
components on the same side as the device, to avoid
routing via through different planes and having compo-
nents on the solder side, as well as absorbing noise from
different planes.
Other general guidelines for signal trace routing include
the following:
— Only differential pair signals should be run par-
allel to each other, since they provide a cancel-
ing effect on noise. However, (non-differential)
parallel traces tend to induce crosstalk. Differ-
ential signal traces should be as short and di-
rect as possible.
— 90 trace corners should be minimized. Bevel
them at a 45-degree angle or as appropriate
(chamfered or radiused approach). Differential
pairs will require equal trace length, even with
45-degree angle traces. Sharp edges add para-
sitic effects that translate into minute impedance
mismatches. At high frequencies, additional
charge accumulation causes an increase in ca-
pacitance at the corners of the trace bend, which
results in a concentration of electric fields.
— Minimize the number of vias for any one given
signal trace. It is recommended that the signal
trace remain only on one plane (component or
solder) or go directly into the power or ground
layer (if it is a power/ground signal). As vias pass
through layers, the impedance of the trace
changes and it is difficult to maintain constant
impedance after the via.
— Traces carrying large amounts of current should
be thicker than normal signal traces. Otherwise,
the traces may be easily burned out by current
overloads.
— Maintain constant trace lengths to avoid imped-
ance mismatch and reflections.
— Avoid long traces, as they generate and pick up
radiated noise from around the board. They also
tend to be a common source of crosstalk.
The system designer can add extra pads that are ca-
pacitor/resistor-sized so that components can be easily
added during the debug stage. The same applies to
IC’s, where some 14/16/18-pin package pads can be
placed on the board to accommodate any changes dur-
ing the debug stage.
To reduce EMI emissions, the following rules should be
observed for board layout:
— The PCB should be multi-layer (4 to 6 layers),
with individual power and ground sublayers for
best high frequency and EMI performance.
Component traces can be run on the component
and solder sides, but preferably only on the com-
ponent side, unless it is absolutely critical to
place decoupling components underneath de-
vices. The power and ground layers should be in
the inner layers of the PCB.
— Proper ground and power plane partitioning (see
below) should be followed, as per recommenda-
tions from transceiver vendors.
— Use shielded components wherever possible.
This refers to RJ-45 jacks, with contacts to chas-
sis ground.
— Proper termination of components and unused
(high speed) pairs in their common mode imped-
ance (to chassis ground) to minimize cable re-
flections and common mode standing waves.
Follow transceiver vendor recommendations.
— When adding spacers to elevate the system
from the chassis, ensure that the screws are not
placed symmetrically (either straight rows/col-
umns or diagonals) throughout the board. The
screws tend to act as antennas and create wave
harmonics that will affect the EMI testing.
Optionally, teflon screws can be used to support
the board.
Clock/Oscillator Considerations
The clock is an equally important device in repeater de-
sign, since it is from the main clock that any reference
clocks (TX_CLK, RX_CLK) are derived, and it is used
for the various PLLs. With a noisy clock signal, PLLs
(even QFEXr’s digital PLL) will have difficulty locking
onto the data packets.
Oscillators are recommended, in the metal can pack-
age, due to the shielding. They should be decoupled as
recommended by manufacturer’s guidelines.
Oscillators should be placed close to repeater and PHY
components, or if not possible, they should be placed
close to the repeater component, and same-length
traces should be used to the QFEXr devices. Traces
should be placed further away from other long traces.
General Rules On Termination
Termination of signals is a requirement in repeater de-
sign. Termination helps reduce ringing/cable reflections
and impedance mismatching. A variety of termination
networks are available, and manufacturer (PHY/
QFEXr, transceiver/MLT-3 and magnetics) recommen-
dations should be heeded.
AC termination is needed to minimize high-speed re-
flections. This can be accomplished by placing a resis-
tor in series with a capacitor to digital ground. This is
recommended on the following signals for the QFEXr
device: RXD[3:0], TXD[3:0], RX_DV, RX_ER, TX_ER,
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