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參數(shù)資料
| 型號： | 21050-AA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 92K |
| 代理商： | 21050-AA |
21050 PCI-to-PCI Bridge Hardware Implementation
Application Note
13
6.0
Arbitration
The following sections describe primary and secondary bus arbitration.
6.1
Primary Bus Arbitration
The 21050 provides request (p_req_l) and grant (p_gnt_l) signals for primary bus access arbitration
in accordance with the PCI Local Bus Specification. These signals connect to external arbiter logic
provided by the system.
6.2
Secondary Bus Arbitration
You can configure the 21050 to use either its internal arbiter or an external arbiter for secondary
bus access arbitration. The 21050 internal secondary bus arbiter supports six bus masters plus the
21050. The 21050 has six request inputs (s_req_l<5:0>) and six grant outputs (s_gnt_l<5:0>).
When the internal arbiter is used, 21050 request and grant lines are internal to the chip.
To use the 21050 secondary bus arbiter:
Tie the central function pin, s_cfn_l, to ground (low) through a 1K resistor.
Connect secondary bus masters to the request and grant line pairs. The 21050has two
arbitration modes, both rotating, so order is not important (initial highest priority is at
s_req_l<0>, however). Tie unused s_req_l input pins high through a 1K resistor. You can leave
unused s_gnt_l output pins unconnected. These signals are compliant with the REQ# and
GNT# specifications in the PCI Local Bus Specification and should be treated accordingly.
The default mode rotates highest priority among all six external bus masters, but gives the
21050 highest priority on alternate transactions. You can select a second mode, which uses
rotating priority among all bus masters including the 21050. Set this alternate mode by writing
a 1 to the Arbitration Mode bit in the 21050 configuration space (Cfg addr 40h, Bit 0).
To use an external secondary bus arbiter:
Tie the central function pin, s_cfn_l, high through a 1K resistor
The 21050 reconfigures the s_req_l<0> and s_gnt_l<0> pins to act as external grant and
request pins. Because s_gnt_l<0> is an output pin, the 21050 uses this pin as an external
secondary bus request line. Connect this pin to one of the request lines of the external arbiter.
Because s_req_l<0> is an input pin, the 21050 uses this pin as an external secondary grant
line. Connect this pin to one of the grant lines of the external arbiter. Tie all s_req_l<5:1> high
through a 1K resistor. You can leave s_gnt_l<5:1> unconnected.
The external arbiter must use some kind of fairness algorithm. If a fixed priority algorithm is
used, a deadlock condition might occur.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 21052-AA | PCI Bus Interface/Controller |
| 21052-AB | PCI Bus Interface/Controller |
| 210600 | KABEL PROFI 3FACH KOAX 75 OHM SW 100M |
| 210602 | KABEL PROFI 3FACH KOAX 75 OHM GRAU 100M |
| 210E | Thermal Probe Multiplexer(熱探頭多路復(fù)用器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 21050AB | 功能描述:IC PCI-PCI BRIDGE 208QFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| 21050-AB | 制造商:Intel 功能描述:IC,BUS CONTROLLER,CMOS,QFP,208PIN |
| 21050D401R00JE | 制造商:OHMITE 制造商全稱:Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
| 21050D401R00KE | 制造商:OHMITE 制造商全稱:Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
| 21050D40250RJE | 制造商:OHMITE 制造商全稱:Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
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