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參數(shù)資料
| 型號： | 21050-AA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 21050-AA |
21050 PCI-to-PCI Bridge Hardware Implementation
10
Application Note
Note:
Some early PCI host bridges automatically claim all configuration commands directed to device 0.
Therefore, it is recommended that you avoid using device 0, if this situation might apply.
5.0
Data Synchronization and Interrupts
The
PCI Local Bus Specification
requires that either the interrupt handler (service routine) or the
device that initiates the interrupt guarantees that all buffers are flushed between the device and the
final destination. To accomplish this, the interrupt service routine of the device driver can perform
a read of the device, or the device itself can perform a read of the last location written by the
device. In either case, the read forces buffers between the device and the final destination to be
flushed.
Interrupts originating from secondary bus devices are not routed through the 21050. However, the
21050 does offer two implementation-specific pins that can be used to implement hardware data
synchronization: s_dispst_l and s_bufne_l. The following sections describe using these data
synchronization pins, and implementing interrupt binding on option cards.
5.1
Using the 21050 Data Synchronization Pins
Although Section 6.3.4 of the
PCI Local Bus Specification
states that device drivers are ultimately
responsible for guaranteeing consistency of data and interrupts, the 21050 does provide a hardware
feature that you can use to synchronize data.
The 21050 implements the following pins:
s_dispst_l (input)
An asserting (falling) edge marks write data currently in both the upstream and downstream
data buffers. If the Disable Posting bit in the 21050 configuration space is set, write posting in
both directions is disabled as long as s_dispst_l remains asserted.
s_bufne_l (output)
This pin is asserted (low) when write data marked by the asserting edge of s_dispst_l remains
in write buffers. s_bufne_l will assert two cycles after s_dispst_l assertion. s_bufne_l deasserts
when all marked posted write data is flushed. This output is always enabled (except during
diagnostics) and does not need a pullup.
Figure 1. Secondary IDSEL Implementation Example
A4884-01
21050
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p_idsel
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PCI Device
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PCI
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 21052-AA | PCI Bus Interface/Controller |
| 21052-AB | PCI Bus Interface/Controller |
| 210600 | KABEL PROFI 3FACH KOAX 75 OHM SW 100M |
| 210602 | KABEL PROFI 3FACH KOAX 75 OHM GRAU 100M |
| 210E | Thermal Probe Multiplexer(熱探頭多路復(fù)用器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 21050AB | 功能描述:IC PCI-PCI BRIDGE 208QFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| 21050-AB | 制造商:Intel 功能描述:IC,BUS CONTROLLER,CMOS,QFP,208PIN |
| 21050D401R00JE | 制造商:OHMITE 制造商全稱:Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
| 21050D401R00KE | 制造商:OHMITE 制造商全稱:Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
| 21050D40250RJE | 制造商:OHMITE 制造商全稱:Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
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