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參數(shù)資料
| 型號(hào)： | 21041 |
| 廠商： | Intel Corp. |
| 英文描述： | Digital Semiconductor 21041 PCI Ethernet LAN Controller(數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)LAN控制器) |
| 中文描述： | 數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)局域網(wǎng)控制器（數(shù)字半導(dǎo)體21041的PCI以太網(wǎng)局域網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 23/64頁(yè) |
| 文件大?。?/td> | 230K |
| 代理商： | 21041 |
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Table 4 (Cont.) Quick Pin Reference
Signal
Type
Pin
Number
Description
irdy_l
I/O
42
Initiator ready indicates the bus initiator’s
ability to complete the current data phase of
the transaction.
A data phase is completed on any clock when
both
irdy_l
and target ready (
trdy_l
) are
asserted. Wait cycles are inserted until both
irdy_l
and
trdy_l
are asserted together.
When the 21041 is the bus initiator,
irdy_l
is
asserted during write operations to indicate
that valid data is present on
ad<31:00>
.
During read operations, the 21041 asserts
irdy_l
to indicate that it is ready to accept
data.
Current reference input for the analog phase-
locked loop (PLL) logic.
Selects either mode 0 (21040) or mode 1
(21041) operation. When this pin is tied to
VSS, mode 0 operation is selected. When
this pin is not connected (internally pulled
up), mode 1 operation is selected. When a
hardware or software reset is detected, the
21041 senses this input and sets the mode of
operation accordingly.
When mode 1 operation is selected, this pin
changes its functionality, and it is actually the
boot ROM or the external register chip enable
(
br_ce_l
) output pin.
Parity is calculated by the 21041 as an even
parity bit for the
ad<31:00>
and
c_be_l<3:0>
lines.
During address and data phases,
par
is
calculated on all the
ad
and
c_be_l
lines
whether or not any of these lines carry
meaningful information.
(continued on next page)
iref
I
86
mode_select
/
br_ce_l
I/O
91
par
I/O
50
15
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