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參數(shù)資料
| 型號(hào)： | 21041 |
| 廠商： | Intel Corp. |
| 英文描述： | Digital Semiconductor 21041 PCI Ethernet LAN Controller(數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)LAN控制器) |
| 中文描述： | 數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)局域網(wǎng)控制器（數(shù)字半導(dǎo)體21041的PCI以太網(wǎng)局域網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 20/64頁(yè) |
| 文件大小： | 230K |
| 代理商： | 21041 |
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Table 4 (Cont.) Quick Pin Reference
Signal
Type
Pin
Number
Description
br_a<0>
/
sr_dout
I/O
79
Boot ROM address line bit 0. In a 256KB
configuration, this pin also carries in two
consecutive address cycles, boot ROM address
bits 16 and 17.
When the 21041 operates with the serial
ROM, serial ROM data out (
sr_dout
) shifts
the Ethernet identification address from the
serial ROM device into the 21041.
During operation with the external register,
this pin is used for read and write control.
Boot ROM address line bit 1. This pin also
latches the boot ROM address and control
lines by the two external latches.
When the 21041 operates with the serial
ROM,
sr_sk
provides the serial ROM clock.
Boot ROM address and data multiplexed lines
bits 6 through 0. In two consecutive address
cycles, these lines contain the boot ROM
address bits 6 through 2,
oe_l
, and
we_l
in
the first cycle; and these lines contain boot
ROM address bits 14 through 8 in the second
cycle. During the data cycles, bits 6 through 0
contain data.
The boot ROM address bits 6 through 0 can
be connected directly to seven network event
LEDs: Transmit, Collision, Receive Address
Matching, Receive, TP Polarity, Transmit
J abber, and LinkPass respectively.
During operation with the external register,
these lines are used to carry data bits 6
through 0 to and from the external register.
(continued on next page)
br_a<1>
/
sr_sk
O
80
br_ad<6:0>
I/O
See
Figure 2.
12
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