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| 型號(hào)： | 20602 |
| 英文描述： | 3.0 Volt-only Flash Memory Technology |
| 中文描述： | 3.0伏只快閃記憶體技術(shù) |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | 20602 |
3.0 Volt-only Technology Background
7
Industry Standard Architecture
AMD’s 3.0 volt-only family of products are based on the same process technology and
industry standard architecture as AMD’s 5.0 volt-only Flash devices. AMD’s process provides
low-power, high-performance CMOS devices using the NOR cell Flash architecture. The
Am29LVxxx family offers the following features:
J
JEDEC single-power-supply standard for pinout and software commands.
J
A memory array that is segmented into smaller sectors for erase operation. This
feature allows for modular code development, storage of boot code, parameters, and
main code in different sectors, and the ability to write protect any or all sectors of the
device.
J
AMD’s Embedded Program and Embedded Erase algorithms that simplify Flash
operation by automating the programming and erase operations on the chip. This
eliminates the need for dedicated CPU control of the device, and thus improves
system-level performance. The embedded algorithms automatically detect and correct
overerase, and eliminate program/erase software implementation errors associated
with first-generation manual algorithm Flash devices.
J
A guaranteed minimum endurance of 1 million program/erase cycles on the 0.35 μm
and new 0.32 μm process technologies. This equates to higher reliability in systems
that rewrite data even once to the Flash device.
Summary
AMD’s 3.0 volt-only design offers all the advantages and performance of its 5.0 volt-only,
industry standard architecture, while providing 3 volt operation optimized for battery-powered
applications. Features of the industry standard architecture include single-power-supply
operation, sector architecture, and Embedded Algorithms. In addition, AMD’s 3.0 volt-only,
Am29LVxxx family of Flash memories provides a 2.7 V to 3.6 V extended operating range
and low power consumption without sacrificing performance.
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