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參數(shù)資料
| 型號(hào)： | 19077 |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 366K |
| 代理商： | 19077 |
Vicor Corp. Tel: 800-735-6200, 978-470-2900 Fax: 978-475-6715
PAC, Phased Array Controller
Rev. 1.2
Page 6 of 8
Set your site on VICOR at vicorpower.com
PARALLEL ARRAY DESIGN
CONSIDERATIONS
Care must be taken to avoid introducing interfering signals
onto the parallel bus as this may prevent synchronous
operation and proper load sharing between modules. One
possible source of interference is input ripple current
conducted via the plus and minus input power pins. The PR
signal and DC power input share a common return which is
the negative input pin. Steps should be taken to de-couple
AC components of input current from the parallel bus. The
input to each converter (designated as + and - pins on the
input side of the module) should be bypassed locally with a
0.2 F ceramic or film capacitor. This provides a shunt path
for input ripple current. A Y-rated capacitor should be
connected between the negative input pin and baseplate of
each module, thus creating a shunt path for common mode
components of current. Attention to the PC board artwork
should minimize the parasitic impedance between negative
input pins of parallel modules to insure that all PR pins are
referenced to the same potential. Modules should be placed
physically close to each other and wide copper traces
(0.75in., 2oz. copper) should be used to connect power input
pins. A dedicated layer of copper is the ideal solution.
Some applications require physical separation of paralleled
modules on different boards, and/or input power from
separate sources. In these cases, transformer coupling of the
PR signal is required to prevent inter-module common mode
“bounce” from interfering with the sync pulse transmission.
High speed buffering may be required if the distance
between modules is greater than a few inches. All modules,
except the one that’s talking, are in the listening mode. Each
listener presents a load which is approximately 500 ohms
shunted by 30 pF capacitance. Long leads for the
interconnection introduce losses and parasitic reactance on
the bus which can attenuate and distort the sync pulse
signal. The bandwidth of the bus must be at least 60 MHz
and the signal attenuation less than 2 dB. In most cases
transformer coupling without buffering is adequate. A
transformer is available (Vicor P/N 22400) for parallel bus
interface that provides SELV isolation and 3000 Vrms
dielectric withstand between windings. This transformer
(Figure 11) is trifiler wound, 1:1:1 turns ratio. One winding
is used, as illustrated in Figure 12 for connection to the
module, and another winding provides the isolated bus
interface to the PAC. Again, careful attention must be given
to layout considerations. Please consult with Applications
Engineering at any Vicor Technical Support Center
(800-927-9474) for additional information.
Figure 10: Conducted Emission Spectrum eight module array delivering 5 V, 500 A.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 190770001 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Avikrimp? Star Ring Tongue Terminal for 18-22 AWG Wire, Stud Size 6 |
| 19077-0001 | 功能描述:端子 STAR RING AVIKRIMP ( VIKRIMP (SRA-829-06) RoHS:否 制造商:AVX 產(chǎn)品:Junction Box - Wire to Wire 系列:9826 線規(guī):26-18 接線柱/接頭大小: 絕緣: 顏色:Red 型式:Female 觸點(diǎn)電鍍:Tin over Nickel 觸點(diǎn)材料:Beryllium Copper, Phosphor Bronze 端接類型:Crimp |
| 190770002 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Avikrimp? Star Ring Tongue Terminal for 18-22 AWG Wire, Stud Size 6, Mylar TapeCarrier |
| 19077-0002 | 功能描述:端子 STAR RING RoHS:否 制造商:AVX 產(chǎn)品:Junction Box - Wire to Wire 系列:9826 線規(guī):26-18 接線柱/接頭大小: 絕緣: 顏色:Red 型式:Female 觸點(diǎn)電鍍:Tin over Nickel 觸點(diǎn)材料:Beryllium Copper, Phosphor Bronze 端接類型:Crimp |
| 190770005 | 制造商:Molex 功能描述:Star Ring Tongue Terminal 18-22AWG 23.62mm 9.78mm Tin Box |
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