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| 型號： | 19077 |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 366K |
| 代理商： | 19077 |
Vicor Corp. Tel: 800-735-6200, 978-470-2900 Fax: 978-475-6715
PAC, Phased Array Controller
Rev. 1.2
Page 4 of 8
Set your site on VICOR at vicorpower.com
System_Reset: The RESET pin is an input pin used to
disable the PAC chip. The system reset also disables the
array by pulling all PC pins low and commanding all PR
pins to assume the high impedance state. The minimum
pulse width required for detection is 1 sec. The PAC
responds asynchronously to the input falling edge, disabling
the internal circuitry of the PAC but not Vcc. The System
Reset employs a Schmitt trigger as an input buffer.
Vcc: The Vcc pin provides an alternate means to power to
the PAC. Alternatively, power may be provided via the PC
pins, which are diode OR’d to the internal Vcc node. Vcc
is the internal supply voltage of the PAC IC. This is
wire-bonded to two pads on the IC, called Vccl (for the
logic) and Vccd (for the drivers). The separate conductors
prevent the high Ldi/dt in the driver stages from disturbing
the analog & digital circuitry in the core. In any
configuration, power may be provided by the external Vcc
pin. The external supply must be capable of supplying
5.0+/-0.5 V@1.5*NmA, where N is the number of
converter modules in the array.
APPLICATIONS INFORMATION
One advantage of the Vicor converter topology is that these
variable frequency, quasi-resonant, zero current switching
DC-DC converter modules lend themselves to a novel load
share scheme based on frequency synchronization. This
method is uniquely compatible with the variable frequency
topology, where line and load regulation is accomplished by
controlling the frequency, or rate at which pulses of energy
are transferred from the primary to the secondary of the
isolation transformer. The pulse width, and therefore the
energy per pulse is constant at any given input voltage.
The pulse repetition rate is therefore representative of
output power, and is controlled to maintain output voltage
regulation while satisfying the load current demand.
It follows therefore that identical converters in a parallel
array will inherently share the load if the switching
frequencies are synchronized. The switching frequency vs
line / load characteristic is uniform to within 5% among
modules of a given type. The PR (parallel) pin on Vicor
Maxi, Mini, Micro Series converter modules is a
bidirectional port which serves as a parallel load share bus.
This port can transmit or receive the synchronizing pulse
signal which is coincident with the leading edge of the
internal power conversion pulse. The controlling module
transmits the sync pulse while all other modules listen.
These converters also posses the ability to self arbitrate the
leadership role. One module always assumes command of
the entire array. If this module experiences a fault condition,
another will take over. The PC pin, which is normally high
(6 V) during operation, switches low in the event that the
module shuts down and periodically toggles high as an
attempt to restart. Transfer of the leadership role is
completely transparent, i.e., the output power bus is
virtually unaffected by the transfer process. This feature
is particularly useful in parallel arrays that employ
redundancy for fault tolerance.
By contrast, the pulsed synchronous current share scheme
offers considerable advantages over commonly used analog
methods, which require either an artificial increase of the
output source impedance of each converter, or a current
sense device at the output of each converter. When using
the Phased Array Controller (PAC), sync pulse processing
produces a sequential and equal distribution of the power
conversion pulses generated by each module in the array.
This in turn eliminates the coherent summation of
conducted and radiated EMI that is associated with the
usual coincident occurrence of energy conversion pulses.
The PAC is able to support up to twelve DC-DC converter
modules and has dedicated input / output ports for
+In
PC
PR
–In
Module 2
+In
PC
PR
–In
Module 1
PC9
28
PR8
27
PC8
26
PR7
25
PC7
24
SYSRES
23
OK
22
PR6
21
PC6
20
PR5
19
PC5
18
PR4
17
PC4
16
PR3
15
PAC
+In
PC
PR
–In
Module 3
(up to 12)
Ground plane
1
PR9
2
PC10
3
PR10
4
PC11
5
PR11
6
PC12
7
PR11
8
Vcc
9
GND
10
PC1
11
PR1
12
PC2
13
PR2
14
PC3
Vcc
Figure 6: Interconnection of the PAC chip with three Vicor
Maxi, Mini, Micro Series DC-DC converters.
Figure 7: The PAC chip supports current sharing
and adjusts the relative phase of each module in the
array in increments of 360°/N, where N is the
number of enabled modules within the array.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 190770001 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Avikrimp? Star Ring Tongue Terminal for 18-22 AWG Wire, Stud Size 6 |
| 19077-0001 | 功能描述:端子 STAR RING AVIKRIMP ( VIKRIMP (SRA-829-06) RoHS:否 制造商:AVX 產(chǎn)品:Junction Box - Wire to Wire 系列:9826 線規(guī):26-18 接線柱/接頭大小: 絕緣: 顏色:Red 型式:Female 觸點電鍍:Tin over Nickel 觸點材料:Beryllium Copper, Phosphor Bronze 端接類型:Crimp |
| 190770002 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Avikrimp? Star Ring Tongue Terminal for 18-22 AWG Wire, Stud Size 6, Mylar TapeCarrier |
| 19077-0002 | 功能描述:端子 STAR RING RoHS:否 制造商:AVX 產(chǎn)品:Junction Box - Wire to Wire 系列:9826 線規(guī):26-18 接線柱/接頭大小: 絕緣: 顏色:Red 型式:Female 觸點電鍍:Tin over Nickel 觸點材料:Beryllium Copper, Phosphor Bronze 端接類型:Crimp |
| 190770005 | 制造商:Molex 功能描述:Star Ring Tongue Terminal 18-22AWG 23.62mm 9.78mm Tin Box |
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