參數(shù)資料
型號: CY39200V388-125MGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: PLD
英文描述: CPLDs at FPGA Densities
中文描述: LOADABLE PLD, 10 ns, PBGA388
封裝: 35 X 35 MM, 1.27 MM PITCH, BGA-388
文件頁數(shù): 41/86頁
文件大?。?/td> 1212K
代理商: CY39200V388-125MGC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 41 of 86
Package Diagrams
51-85069-*B
208-Lead Enhanced Quad Flat Pack (EQFP) NT208
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參數(shù)描述
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