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參數資料
| 型號： | 16SP100M |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Synchronous Buck Controller with Pre-bias Startup, and Optional Clock Synchronization |
| 中文描述： | 同步降壓控制器，帶有預偏置啟動和可選時鐘同步 |
| 文件頁數： | 18/23頁 |
| 文件大小： | 1002K |
| 代理商： | 16SP100M |
Application Information
(Continued)
In practice, a good trade off between phase margin and
bandwidth can be obtained by selecting the closest
±
10%
capacitor values above what are suggested for C
and C
,
the closest
±
10% capacitor value below the suggestion for
C
, and the closest
±
1% resistor values below the sugges-
tions for R
, R
C2
. Note that if the suggested value for R
is
less than 100
, it should be replaced by a short circuit.
Following this guideline, the compensation components will
be:
C
C1
= 27 pF
±
10%, C
C2
= 820 pF
±
10%
C
C3
= 2.7 nF
±
10%, R
C1
= 39.2 k
±
1%
R
C2
= 2.55 k
±
1%
The transfer function of the compensation block can be
derived by considering the compensation components as
impedance blocks Z
F
and Z
I
around an inverting op-amp:
As with the generic equation, G
must be modified
to take into account the limited bandwidth of the error ampli-
fier. The result is:
The total control loop transfer function H is equal to the
power stage transfer function multiplied by the error amplifier
transfer function.
H = G
PS
x H
EA
The bandwidth and phase margin can be read graphically
from Bode plots of H
EA
as shown in
Figure 16
.
The bandwidth of this example circuit is 59 kHz, with a phase
margin of 60.
EFFICIENCY CALCULATIONS
The following is a sample calculation.
A reasonable estimation of the efficiency of a switching buck
controller can be obtained by adding together the Output
Power (P
OUT
) loss and the Total Power (P
TOTAL
) loss:
The Output Power (P
) for the Typical Application Circuit
design is (1.2V x 4A) = 4.8W. The Total Power (P
), with
an efficiency calculation to complement the design, is shown
below.
The majority of the power losses are due to the low side and
high side MOSFET’s losses. The losses in any MOSFET are
group of switching (P
SW
) and conduction losses (P
CND
).
P
FET
= P
SW
+ P
CND
= 61.38 mW + 270.42 mW
P
FET
= 331.8 mW
FET Switching Loss (P
SW
)
P
SW
= P
SW(ON)
+ P
SW(OFF)
P
SW
= 0.5 x V
IN
x I
OUT
x (t
r
+ t
f
) x f
SW
20150985
20150986
FIGURE 16. Overall Loop Gain and Phase
L
www.national.com
18
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