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參數(shù)資料
| 型號： | 16F877 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE GREEN 20 FT |
| 中文描述： | 28/40-pin 8位CMOS閃存微控制器 |
| 文件頁數(shù)： | 77/200頁 |
| 文件大?。?/td> | 3544K |
| 代理商： | 16F877 |
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PIC16F87X
1999 Microchip Technology Inc.
DS30292A-page 77
9.2.6
MULTI-MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the MSSP module is disabled. Control of the I
2
C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored for abitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
9.2.7
I
2
C MASTER MODE SUPPORT
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once master mode is enabled, the user
has six options.
- Assert a start condition on SDA and SCL.
- Assert a Repeated Start condition on SDA and
SCL.
- Write to the SSPBUF register initiating trans-
mission of data/address.
- Generate a stop condition on SDA and SCL.
- Configure the I
2
C port to receive data.
- Generate an Acknowledge condition at the end
of a received byte of data.
The MSSP Module, when configured in I
2
C
Master Mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a start condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
9.2.7.1
I
2
C MASTER MODE OPERATION
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
Start condition. Since the Repeated Start condition is
also the beginning of the next serial transfer, the I
2
C
bus will not be released.
In Master Transmitter mode serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I
2
C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the SSP-
BUF. Once the given operation is complete (i.e. trans-
mission of the last data bit is followed by ACK) the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
A typical transmit sequence would go as follows:
a)
The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
b)
SSPIF is set. The module will wait the required
start time before any other operation takes
place.
c)
The user loads the SSPBUF with address to
transmit.
d)
Address is shifted out the SDA pin until all 8 bits
are transmitted.
e)
The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register ( SSPCON2<6>).
f)
The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g)
The user loads the SSPBUF with eight bits of
data.
h)
DATA is shifted out the SDA pin until all 8 bits
are transmitted.
Note:
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