參數(shù)資料
型號： 16F877
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 20 FT
中文描述： 28/40-pin 8位CMOS閃存微控制器
文件頁數(shù)： 185/200頁
文件大?。?/td> 3544K
代理商： 16F877
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PIC16F87X
1999 Microchip Technology Inc.
DS30292B-page 185
INDEX
A
A/D ...................................................................................111
ADCON0 Register ....................................................111
ADCON1 Register ....................................................112
ADIF bit ....................................................................113
Analog Input Model Block Diagram ..........................115
Analog Port Pins ......................................7, 8, 9, 37, 38
Block Diagram ..........................................................114
Configuring Analog Port Pins ...................................116
Configuring the Interrupt ..........................................113
Configuring the Module ............................................113
Conversion Clock .....................................................116
Conversions .............................................................117
Delays ......................................................................115
Effects of a Reset .....................................................118
GO/DONE bit ...........................................................113
Internal Sampling Switch (Rss) Impedence .............114
Operation During Sleep ...........................................118
Sampling Requirements ...........................................114
Source Impedence ...................................................114
Time Delays .............................................................115
Absolute Maximum Ratings .............................................151
ACK ....................................................................................72
Acknowledge Data bit ........................................................66
Acknowledge Pulse ............................................................72
Acknowledge Sequence Enable bit ...................................66
Acknowledge Status bit ......................................................66
ADRES Register ........................................................15, 111
Application Note AN578, "Use of the SSP Module
in the I2C Multi-Master Environment." ...............................71
Application Notes
AN552 (Implementing Wake-up on Key
Strokes Using PIC16CXXX) .......................................31
AN556 (Table Reading Using PIC16CXX) .................26
Architecture
PIC16F873/PIC16F876 Block Diagram .......................5
PIC16F874/PIC16F877 Block Diagram .......................6
Assembler
MPASM Assembler ..................................................145
B
Banking, Data Memory ................................................12, 18
Baud Rate Generator .........................................................78
BCLIF .................................................................................24
BF ....................................................................64, 72, 81, 83
Block Diagrams
A/D ...........................................................................114
Analog Input Model ..................................................115
Baud Rate Generator .................................................78
Capture ......................................................................59
Compare ....................................................................60
I
2
C Master Mode ........................................................76
I
2
C Module .................................................................71
PWM ..........................................................................60
SSP (I
2
C Mode) .........................................................71
SSP (SPI Mode) .........................................................67
Timer0/WDT Prescaler ..............................................47
Timer2 ........................................................................55
USART Receive .......................................................101
USART Transmit ........................................................99
BRG ...................................................................................78
BRGH bit ............................................................................97
Brown-out Reset (BOR) ...........................121, 125, 127, 128
BOR Status (BOR Bit) ................................................25
Buffer Full bit, BF ............................................................... 72
Buffer Full Status bit, BF .................................................... 64
Bus Arbitration ................................................................... 88
Bus Collision Section ......................................................... 88
Bus Collision During a RESTART Condition ..................... 91
Bus Collision During a Start Condition ............................... 89
Bus Collision During a Stop Condition ............................... 92
Bus Collision Interrupt Flag bit, BCLIF ............................... 24
C
Capture/Compare/PWM
Capture
Block Diagram ................................................... 59
CCP1CON Register ........................................... 58
CCP1IF .............................................................. 59
Mode ................................................................. 59
Prescaler ........................................................... 59
CCP Timer Resources ............................................... 57
Compare
Block Diagram ................................................... 60
Mode ................................................................. 60
Software Interrupt Mode .................................... 60
Special Event Trigger ........................................ 60
Special Trigger Output of CCP1 ........................ 60
Special Trigger Output of CCP2 ........................ 60
Interaction of Two CCP Modules ............................... 57
Section ....................................................................... 57
Special Event Trigger and A/D Conversions ............. 60
Capture/Compare/PWM (CCP)
CCP1
RC2/CCP1 Pin ................................................. 7, 8
CCP2
RC1/T1OSI/CCP2 Pin ..................................... 7, 8
PWM Block Diagram ................................................. 60
PWM Mode ................................................................ 60
CCP1CON ......................................................................... 17
CCP2CON ......................................................................... 17
CCPR1H Register .................................................. 15, 17, 57
CCPR1L Register ........................................................ 17, 57
CCPR2H Register ........................................................ 15, 17
CCPR2L Register ........................................................ 15, 17
CCPxM0 bit ........................................................................ 58
CCPxM1 bit ........................................................................ 58
CCPxM2 bit ........................................................................ 58
CCPxM3 bit ........................................................................ 58
CCPxX bit .......................................................................... 58
CCPxY bit .......................................................................... 58
CKE ................................................................................... 64
CKP ................................................................................... 65
Clock Polarity Select bit, CKP ............................................ 65
Code Examples
Call of a Subroutine in Page 1 from Page 0 .............. 26
Indirect Addressing .................................................... 27
Code Protection ....................................................... 121, 135
Computed GOTO ............................................................... 26
Configuration Bits ............................................................ 121
Conversion Considerations .............................................. 183
D
D/A ..................................................................................... 64
Data Memory ..................................................................... 12
Bank Select (RP1:RP0 Bits) ................................ 12, 18
General Purpose Registers ....................................... 12
Register File Map ................................................ 13, 14
Special Function Registers ........................................ 15
Data/Address bit, D/A ........................................................ 64
DC Characteristics ........................................................... 154
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