參數(shù)資料
型號： 16F628
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE BLUE 1 FT
中文描述： 基于閃存的8位CMOS微控制器
文件頁數(shù)： 45/168頁
文件大?。?/td> 3760K
代理商： 16F628
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 43
PIC16F627A/628A/648A
TABLE 5-3:
PORTB FUNCTIONS
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
(1)
Name
Function
Input Type
Output
Type
Description
RB0/INT
RB0
TTL
CMOS
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
INT
ST
—
External interrupt.
RB1/RX/DT
RB1
TTL
CMOS
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
RX
ST
—
USART Receive Pin
DT
ST
CMOS
Synchronous data I/O
RB2/TX/CK
RB2
TTL
CMOS
Bi-directional I/O port
TX
—
CMOS
USART Transmit Pin
CK
ST
CMOS
Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
RB3/CCP1
RB3
TTL
CMOS
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
CCP1
ST
CMOS
Capture/Compare/PWM/I/O
RB4/PGM
RB4
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
PGM
ST
—
Low voltage programming input pin. When low voltage
programming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
RB5
RB5
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
RB6/T1OSO/T1CKI/
PGC
RB6
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T1OSO
—
XTAL
Timer1 Oscillator Output
T1CKI
ST
—
Timer1 Clock Input
PGC
ST
—
ICSP Programming Clock
RB7/T1OSI/PGD
RB7
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T1OSI
XTAL
—
Timer1 Oscillator Input
PGD
ST
CMOS
ICSP Data I/O
Legend: O = Output
— = Not used
TTL = TTL Input
CMOS = CMOS Output
I
= Input
OD
= Open Drain Output
P
ST = Schmitt Trigger Input
AN = Analog
= Power
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
06h, 106h
PORTB
RB7
RB6
RB5
RB4
(2)
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
86h, 186h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
81h, 181h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Legend: u = unchanged, x = unknown
Note
1:
Shaded bits are not used by PORTB.
2:
LVP Configuration Bit sets RB4 functionality.
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